1 ::::::::::::::::::::::::::::::::::::::::::::::::::
2 :: ::
3 :: Covered -- Verilog Coverage Verbose Report ::
4 :: ::
5 ::::::::::::::::::::::::::::::::::::::::::::::::::
6
7
8 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GENERAL INFORMATION ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 * Report generated from CDD file : example.cdd
12
13 * Reported by : Module
14
15 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ LINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
17 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 Module Filename Hit/ Miss/Total Percent hit
19 ---------------------------------------------------------------------------------------------------------------------
20 main example.v 1/ 0/ 1 100%
21 fsma example.v 6/ 0/ 6 100%
22 fsmb example.v 5/ 1/ 6 83%
23 ---------------------------------------------------------------------------------------------------------------------
24
25 Module: fsmb, File: example.v
26 -------------------------------------------------------------------------------------------------------------
27 Missed Lines
28
29 80: next_state = 3'b1
30
31
32
33 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
34 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TOGGLE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
35 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
36 Module Filename Toggle 0 -> 1 Toggle 1 -> 0
37 Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
38 ---------------------------------------------------------------------------------------------------------------------
39 main example.v 4/ 2/ 6 67% 3/ 3/ 6 50%
40 fsma example.v 5/ 3/ 8 62% 4/ 4/ 8 50%
41 fsmb example.v 4/ 4/ 8 50% 3/ 5/ 8 38%
42 ---------------------------------------------------------------------------------------------------------------------
43
44 Module: main, File: example.v
45 -------------------------------------------------------------------------------------------------------------
46 Signals not getting 100% toggle coverage
47
48 Signal Toggle
49 ---------------------------------------------------------------------------------------------------------
50 go 0->1: 1'h1
51 ......................... 1->0: 1'h0 ...
52 state 0->1: 3'h3
53 ......................... 1->0: 3'h5 ...
54 error 0->1: 1'h0
55 ......................... 1->0: 1'h0 ...
56
57 Module: fsma, File: example.v
58 -------------------------------------------------------------------------------------------------------------
59 Signals not getting 100% toggle coverage
60
61 Signal Toggle
62 ---------------------------------------------------------------------------------------------------------
63 go 0->1: 1'h1
64 ......................... 1->0: 1'h0 ...
65 state 0->1: 3'h3
66 ......................... 1->0: 3'h5 ...
67 next_state 0->1: 3'h2
68 ......................... 1->0: 3'h1 ...
69
70 Module: fsmb, File: example.v
71 -------------------------------------------------------------------------------------------------------------
72 Signals not getting 100% toggle coverage
73
74 Signal Toggle
75 ---------------------------------------------------------------------------------------------------------
76 go 0->1: 1'h1
77 ......................... 1->0: 1'h0 ...
78 next_state 0->1: 3'h2
79 ......................... 1->0: 3'h1 ...
80 state 0->1: 3'h2
81 ......................... 1->0: 3'h1 ...
82
83
84 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ COMBINATIONAL LOGIC COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
86 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
87 Module Filename Logical Combinations
88 Hit/Miss/Total Percent hit
89 ---------------------------------------------------------------------------------------------------------------------
90 main example.v 11/ 8/ 19 58%
91 fsma example.v 13/ 5/ 18 72%
92 fsmb example.v 13/ 5/ 18 72%
93 ---------------------------------------------------------------------------------------------------------------------
94
95 Module: main, File: example.v
96 -------------------------------------------------------------------------------------------------------------
97 Missed Combinations (* = missed value)
98
99 =========================================================================================================
100 Line # Expression
101 =========================================================================================================
102 14: error = ((state[0] & state[1]) || (state[0] & state[2]) || (state[1] & state[2]) || (state == 3'b0))
103 |---------1---------| |---------2---------| |---------3---------| |------4------|
104 |--------------------------------------------5---------------------------------------------|
105
106 Expression 1 (3/4)
107 ^^^^^^^^^^^^^ - &
108 LR | LR | LR | LR
109 =00=|=01=|=10=|=11=
110 *
111
112 Expression 2 (3/4)
113 ^^^^^^^^^^^^^ - &
114 LR | LR | LR | LR
115 =00=|=01=|=10=|=11=
116 *
117
118 Expression 3 (3/4)
119 ^^^^^^^^^^^^^ - &
120 LR | LR | LR | LR
121 =00=|=01=|=10=|=11=
122 *
123
124 Expression 4 (1/2)
125 ^^^^^^^^^^^^^ - ==
126 E | E
127 =0=|=1=
128 *
129
130 Expression 5 (1/5)
131 ^^^^^^^^^^^^^ - ||
132 1 | 2 | 3 | 4 | All
133 =1=|=1=|=1=|=1=|==0==
134 * * * *
135
136
137 Module: fsma, File: example.v
138 -------------------------------------------------------------------------------------------------------------
139 Missed Combinations (* = missed value)
140
141 =========================================================================================================
142 Line # Expression
143 =========================================================================================================
144 46: state <= next_state
145 |---1----|
146
147 Expression 1 (1/2)
148 ^^^^^^^^^^^^^ -
149 E | E
150 =0=|=1=
151 *
152
153 =========================================================================================================
154 Line # Expression
155 =========================================================================================================
156 51: case( state )
157 |-1-|
158 3'b1 :
159
160 Expression 1 (1/2)
161 ^^^^^^^^^^^^^ -
162 E | E
163 =0=|=1=
164 *
165
166 =========================================================================================================
167 Line # Expression
168 =========================================================================================================
169 51: next_state = go ? 3'b10 : 3'b1
170 |-------1--------|
171
172 Expression 1 (1/2)
173 ^^^^^^^^^^^^^ - ?:
174 E | E
175 =0=|=1=
176 *
177
178 =========================================================================================================
179 Line # Expression
180 =========================================================================================================
181 52: next_state = go ? 3'b10 : 3'b100
182 |1|
183 |--------2---------|
184
185 Expression 1 (1/2)
186 ^^^^^^^^^^^^^ -
187 E | E
188 =0=|=1=
189 *
190
191 Expression 2 (1/2)
192 ^^^^^^^^^^^^^ - ?:
193 E | E
194 =0=|=1=
195 *
196
197
198 Module: fsmb, File: example.v
199 -------------------------------------------------------------------------------------------------------------
200 Missed Combinations (* = missed value)
201
202 =========================================================================================================
203 Line # Expression
204 =========================================================================================================
205 70: state <= next_state
206 |---1----|
207
208 Expression 1 (1/2)
209 ^^^^^^^^^^^^^ -
210 E | E
211 =0=|=1=
212 *
213
214 =========================================================================================================
215 Line # Expression
216 =========================================================================================================
217 78: case( state )
218 |-1-|
219 3'b1 :
220
221 Expression 1 (1/2)
222 ^^^^^^^^^^^^^ -
223 E | E
224 =0=|=1=
225 *
226
227 =========================================================================================================
228 Line # Expression
229 =========================================================================================================
230 78: next_state = go ? 3'b10 : 3'b1
231 |-------1--------|
232
233 Expression 1 (1/2)
234 ^^^^^^^^^^^^^ - ?:
235 E | E
236 =0=|=1=
237 *
238
239 =========================================================================================================
240 Line # Expression
241 =========================================================================================================
242 79: next_state = go ? 3'b10 : 3'b100
243 |1|
244 |--------2---------|
245
246 Expression 1 (1/2)
247 ^^^^^^^^^^^^^ -
248 E | E
249 =0=|=1=
250 *
251
252 Expression 2 (1/2)
253 ^^^^^^^^^^^^^ - ?:
254 E | E
255 =0=|=1=
256 *
257
258
259
260 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
261 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ FINITE STATE MACHINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
262 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
263 State Arc
264 Module Filename Hit/Miss/Total Percent Hit Hit/Miss/Total Percent hit
265 ---------------------------------------------------------------------------------------------------------------------
266 main example.v 0/ 0/ 0 100% 0/ 0/ 0 100%
267 fsma example.v 2/ ? / ? ? % 2/ ? / ? ? %
268 fsmb example.v 2/ 1/ 3 67% 2/ 2/ 4 50%
269 ---------------------------------------------------------------------------------------------------------------------
270
271 Module: fsma, File: example.v
272 -------------------------------------------------------------------------------------------------------------
273 FSM input state (state), output state (next_state)
274
275 Hit States
276
277 States
278 ======
279 3'h1
280 3'h2
281
282 Hit State Transitions
283
284 From State To State
285 ========== ==========
286 3'h1 -> 3'h1
287 3'h1 -> 3'h2
288
289
290 Module: fsmb, File: example.v
291 -------------------------------------------------------------------------------------------------------------
292 FSM input state (state), output state (next_state)
293
294 Missed States
295
296 States
297 ======
298 3'h4
299
300 Missed State Transitions
301
302 From State To State
303 ========== ==========
304 3'h2 -> 3'h4
305 3'h4 -> 3'h1
306
307
308
309