1 ::::::::::::::::::::::::::::::::::::::::::::::::::
2 :: ::
3 :: Covered -- Verilog Coverage Verbose Report ::
4 :: ::
5 ::::::::::::::::::::::::::::::::::::::::::::::::::
6
7
8 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GENERAL INFORMATION ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 * Report generated from CDD file : cov.cdd
12
13 * Reported by : Instance
14
15 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ LINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
17 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18 Instance Hit/ Miss/Total Percent hit
19 ---------------------------------------------------------------------------------------------------------------------
20 $root 0/ 0/ 0 100%
21 main 6/ 1/ 7 86%
22 main.fsm1 4/ 0/ 4 100%
23 main.fsm2 3/ 1/ 4 75%
24 ---------------------------------------------------------------------------------------------------------------------
25
26 Module: main, File: example.v, Instance: main
27 -------------------------------------------------------------------------------------------------------------
28 Missed Lines
29
30 22: err_cnt = (err_cnt + 1)
31
32
33 Module: fsmb, File: example.v, Instance: main.fsm2
34 -------------------------------------------------------------------------------------------------------------
35 Missed Lines
36
37 92: next_state = 3'b1
38
39
40
41 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
42 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TOGGLE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
43 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
44 Instance Toggle 0 -> 1 Toggle 1 -> 0
45 Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
46 ---------------------------------------------------------------------------------------------------------------------
47 $root 0/ 0/ 0 100% 0/ 0/ 0 100%
48 main 4/ 6/ 10 40% 3/ 7/ 10 30%
49 main.fsm1 5/ 3/ 8 62% 4/ 4/ 8 50%
50 main.fsm2 4/ 4/ 8 50% 3/ 5/ 8 38%
51 ---------------------------------------------------------------------------------------------------------------------
52
53 Module: main, File: example.v, Instance: main
54 -------------------------------------------------------------------------------------------------------------
55 Signals not getting 100% toggle coverage
56
57 Signal Toggle
58 ---------------------------------------------------------------------------------------------------------
59 go 0->1: 1'h1
60 ......................... 1->0: 1'h0 ...
61 state 0->1: 3'h3
62 ......................... 1->0: 3'h5 ...
63 err_cnt 0->1: 5'h00
64 ......................... 1->0: 5'h00 ...
65
66 Module: fsma, File: example.v, Instance: main.fsm1
67 -------------------------------------------------------------------------------------------------------------
68 Signals not getting 100% toggle coverage
69
70 Signal Toggle
71 ---------------------------------------------------------------------------------------------------------
72 go 0->1: 1'h1
73 ......................... 1->0: 1'h0 ...
74 state 0->1: 3'h3
75 ......................... 1->0: 3'h5 ...
76 next_state 0->1: 3'h2
77 ......................... 1->0: 3'h1 ...
78
79 Module: fsmb, File: example.v, Instance: main.fsm2
80 -------------------------------------------------------------------------------------------------------------
81 Signals not getting 100% toggle coverage
82
83 Signal Toggle
84 ---------------------------------------------------------------------------------------------------------
85 go 0->1: 1'h1
86 ......................... 1->0: 1'h0 ...
87 next_state 0->1: 3'h2
88 ......................... 1->0: 3'h1 ...
89 state 0->1: 3'h2
90 ......................... 1->0: 3'h1 ...
91
92
93 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
94 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MEMORY COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
95 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
96 Toggle 0 -> 1 Toggle 1 -> 0
97 Instance Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
98 ---------------------------------------------------------------------------------------------------------------------
99 $root 0/ 0/ 0 100% 0/ 0/ 0 100%
100 main 0/ 64/ 64 0% 0/ 64/ 64 0%
101 main.fsm1 0/ 0/ 0 100% 0/ 0/ 0 100%
102 main.fsm2 0/ 0/ 0 100% 0/ 0/ 0 100%
103
104 Addressable elements written Addressable elements read
105 Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
106 ---------------------------------------------------------------------------------------------------------------------
107 $root 0/ 0/ 0 100% 0/ 0/ 0 100%
108 main 1/ 15/ 16 6% 1/ 15/ 16 6%
109 main.fsm1 0/ 0/ 0 100% 0/ 0/ 0 100%
110 main.fsm2 0/ 0/ 0 100% 0/ 0/ 0 100%
111 ---------------------------------------------------------------------------------------------------------------------
112
113 Module: main, File: example.v, Instance: main
114 -------------------------------------------------------------------------------------------------------------
115 Memories not getting 100% coverage
116
117 ---------------------------------------------------------------------------------------------------------
118 Memory name: err_mem[0:15]
119 ---------------------------------------------------------------------------------------------------------
120 err_mem[0] Written: 1 0->1: 4'h0
121 .......... Read : 1 1->0: 4'h0 ...
122 err_mem[1] Written: 0 0->1: 4'h0
123 .......... Read : 0 1->0: 4'h0 ...
124 err_mem[2] Written: 0 0->1: 4'h0
125 .......... Read : 0 1->0: 4'h0 ...
126 err_mem[3] Written: 0 0->1: 4'h0
127 .......... Read : 0 1->0: 4'h0 ...
128 err_mem[4] Written: 0 0->1: 4'h0
129 .......... Read : 0 1->0: 4'h0 ...
130 err_mem[5] Written: 0 0->1: 4'h0
131 .......... Read : 0 1->0: 4'h0 ...
132 err_mem[6] Written: 0 0->1: 4'h0
133 .......... Read : 0 1->0: 4'h0 ...
134 err_mem[7] Written: 0 0->1: 4'h0
135 .......... Read : 0 1->0: 4'h0 ...
136 err_mem[8] Written: 0 0->1: 4'h0
137 .......... Read : 0 1->0: 4'h0 ...
138 err_mem[9] Written: 0 0->1: 4'h0
139 .......... Read : 0 1->0: 4'h0 ...
140 err_mem[10] Written: 0 0->1: 4'h0
141 ........... Read : 0 1->0: 4'h0 ...
142 err_mem[11] Written: 0 0->1: 4'h0
143 ........... Read : 0 1->0: 4'h0 ...
144 err_mem[12] Written: 0 0->1: 4'h0
145 ........... Read : 0 1->0: 4'h0 ...
146 err_mem[13] Written: 0 0->1: 4'h0
147 ........... Read : 0 1->0: 4'h0 ...
148 err_mem[14] Written: 0 0->1: 4'h0
149 ........... Read : 0 1->0: 4'h0 ...
150 err_mem[15] Written: 0 0->1: 4'h0
151 ........... Read : 0 1->0: 4'h0 ...
152
153
154 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
155 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ COMBINATIONAL LOGIC COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
156 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
157 Instance Logic Combinations
158 Hit/Miss/Total Percent hit
159 ---------------------------------------------------------------------------------------------------------------------
160 $root 0/ 0/ 0 100%
161 main 14/ 11/ 25 56%
162 main.fsm1 8/ 4/ 12 67%
163 main.fsm2 8/ 4/ 12 67%
164 ---------------------------------------------------------------------------------------------------------------------
165
166 Module: main, File: example.v, Instance: main
167 -------------------------------------------------------------------------------------------------------------
168 Missed Combinations (* = missed value)
169
170 =========================================================================================================
171 Line # Expression
172 =========================================================================================================
173 20: err_mem[err_cnt] = {(state[0] & state[1]), (state[0] & state[2]), (state[1] & state[2]), (state == 3'b0)}
174 |---------1---------| |---------2---------| |---------3---------| |------4------|
175 |-----------------------------------------5------------------------------------------|
176
177 Expression 1 (2/3)
178 ^^^^^^^^^^^^^ - &
179 LR | LR | LR
180 =0-=|=-0=|=11=
181 *
182
183 Expression 2 (2/3)
184 ^^^^^^^^^^^^^ - &
185 LR | LR | LR
186 =0-=|=-0=|=11=
187 *
188
189 Expression 3 (2/3)
190 ^^^^^^^^^^^^^ - &
191 LR | LR | LR
192 =0-=|=-0=|=11=
193 *
194
195 Expression 4 (1/2)
196 ^^^^^^^^^^^^^ - ==
197 E | E
198 =0=|=1=
199 *
200
201 Expression 5 (1/2)
202 ^^^^^^^^^^^^^ - {}
203 E | E
204 =0=|=1=
205 *
206
207 =========================================================================================================
208 Line # Expression
209 =========================================================================================================
210 21: if( (!err_cnt[4] && (err_mem[err_cnt] != 0)) )
211 |----1----| |----------2----------|
212 |------------------3-------------------|
213
214 Expression 1 (1/2)
215 ^^^^^^^^^^^^^ - !
216 E | E
217 =0=|=1=
218 *
219
220 Expression 2 (1/2)
221 ^^^^^^^^^^^^^ - !=
222 E | E
223 =0=|=1=
224 *
225
226 Expression 3 (1/3)
227 ^^^^^^^^^^^^^ - &&
228 LR | LR | LR
229 =0-=|=-0=|=11=
230 * *
231
232 =========================================================================================================
233 Line # Expression
234 =========================================================================================================
235 22: err_cnt = (err_cnt + 1)
236 |-----1-----|
237
238 Expression 1 (0/2)
239 ^^^^^^^^^^^^^ - +
240 E | E
241 =0=|=1=
242 * *
243
244
245 Module: fsma, File: example.v, Instance: main.fsm1
246 -------------------------------------------------------------------------------------------------------------
247 Missed Combinations (* = missed value)
248
249 =========================================================================================================
250 Line # Expression
251 =========================================================================================================
252 61: case( state )
253 |-1-|
254 3'b1 :
255
256 Expression 1 (1/2)
257 ^^^^^^^^^^^^^ -
258 E | E
259 =0=|=1=
260 *
261
262 =========================================================================================================
263 Line # Expression
264 =========================================================================================================
265 61: next_state = go ? 3'b10 : 3'b1
266 |-------1--------|
267
268 Expression 1 (1/2)
269 ^^^^^^^^^^^^^ - ?:
270 E | E
271 =0=|=1=
272 *
273
274 =========================================================================================================
275 Line # Expression
276 =========================================================================================================
277 62: next_state = go ? 3'b10 : 3'b100
278 |1|
279 |--------2---------|
280
281 Expression 1 (1/2)
282 ^^^^^^^^^^^^^ -
283 E | E
284 =0=|=1=
285 *
286
287 Expression 2 (1/2)
288 ^^^^^^^^^^^^^ - ?:
289 E | E
290 =0=|=1=
291 *
292
293
294 Module: fsmb, File: example.v, Instance: main.fsm2
295 -------------------------------------------------------------------------------------------------------------
296 Missed Combinations (* = missed value)
297
298 =========================================================================================================
299 Line # Expression
300 =========================================================================================================
301 90: case( state )
302 |-1-|
303 3'b1 :
304
305 Expression 1 (1/2)
306 ^^^^^^^^^^^^^ -
307 E | E
308 =0=|=1=
309 *
310
311 =========================================================================================================
312 Line # Expression
313 =========================================================================================================
314 90: next_state = go ? 3'b10 : 3'b1
315 |-------1--------|
316
317 Expression 1 (1/2)
318 ^^^^^^^^^^^^^ - ?:
319 E | E
320 =0=|=1=
321 *
322
323 =========================================================================================================
324 Line # Expression
325 =========================================================================================================
326 91: next_state = go ? 3'b10 : 3'b100
327 |1|
328 |--------2---------|
329
330 Expression 1 (1/2)
331 ^^^^^^^^^^^^^ -
332 E | E
333 =0=|=1=
334 *
335
336 Expression 2 (1/2)
337 ^^^^^^^^^^^^^ - ?:
338 E | E
339 =0=|=1=
340 *
341
342
343
344 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
345 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ FINITE STATE MACHINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
346 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
347 State Arc
348 Instance Hit/Miss/Total Percent hit Hit/Miss/Total Percent hit
349 ---------------------------------------------------------------------------------------------------------------------
350 $root 0/ 0/ 0 100% 0/ 0/ 0 100%
351 main 0/ 0/ 0 100% 0/ 0/ 0 100%
352 main.fsm1 3/ ? / ? ? % 4/ ? / ? ? %
353 main.fsm2 2/ 1/ 3 67% 3/ 2/ 5 60%
354 ---------------------------------------------------------------------------------------------------------------------
355
356 Module: fsma, File: example.v, Instance: main.fsm1
357 -------------------------------------------------------------------------------------------------------------
358 FSM input state (state), output state (next_state)
359
360 Hit States
361
362 States
363 ======
364 3'h4
365 3'h1
366 3'h2
367
368 Hit State Transitions
369
370 From State To State
371 ========== ==========
372 3'h4 -> 3'h1
373 3'h1 -> 3'h1
374 3'h1 -> 3'h2
375 3'h2 -> 3'h2
376
377
378 Module: fsmb, File: example.v, Instance: main.fsm2
379 -------------------------------------------------------------------------------------------------------------
380 FSM input state (state), output state (next_state)
381
382 Missed States
383
384 States
385 ======
386 3'h4
387
388 Missed State Transitions
389
390 From State To State
391 ========== ==========
392 3'h2 -> 3'h4
393 3'h4 -> 3'h1
394
395
396
397 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
398 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ASSERTION COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
399 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
400 Instance Hit/ Miss/Total Percent hit
401 ---------------------------------------------------------------------------------------------------------------------
402 $root 0/ 0/ 0 100%
403 main 0/ 0/ 0 100%
404 main.fsm1 2/ 0/ 2 100%
405 main.fsm2 1/ 1/ 2 50%
406 ---------------------------------------------------------------------------------------------------------------------
407
408 Module: fsmb, File: example.v, Instance: main.fsm2
409 -------------------------------------------------------------------------------------------------------------
410 Missed Assertions
411
412 Instance Name Assertion Name Coverage Point
413 ---------------------------------------------------------------------------------------------------------
414 zzz_check_state assert_one_hot "all_one_hots_checked covered "
415
416
417
418 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
419 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ RACE CONDITION VIOLATIONS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
420 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
421 Module Filename Number of Violations found
422 ---------------------------------------------------------------------------------------------------------------------
423 $root NA 0
424 main example.v 0
425 fsma example.v 1
426 fsmb example.v 1
427 ---------------------------------------------------------------------------------------------------------------------
428
429 Module: fsma, File: example.v
430 -------------------------------------------------------------------------------------------------------------
431 Starting Line # Race Condition Violation Reason
432 ---------------------------------------------------------------------------------------------------------
433 56: Signal assigned in two different statement blocks
434
435
436 Module: fsmb, File: example.v
437 -------------------------------------------------------------------------------------------------------------
438 Starting Line # Race Condition Violation Reason
439 ---------------------------------------------------------------------------------------------------------
440 82: Signal assigned in two different statement blocks
441
442
443