LLVM API Documentation

HexagonMachineFunctionInfo.h
Go to the documentation of this file.
00001 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 
00010 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
00011 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
00012 
00013 #include "llvm/CodeGen/MachineFunction.h"
00014 #include <map>
00015 
00016 namespace llvm {
00017 
00018   namespace Hexagon {
00019     const unsigned int StartPacket = 0x1;
00020     const unsigned int EndPacket = 0x2;
00021   }
00022 
00023 
00024 /// Hexagon target-specific information for each MachineFunction.
00025 class HexagonMachineFunctionInfo : public MachineFunctionInfo {
00026   // SRetReturnReg - Some subtargets require that sret lowering includes
00027   // returning the value of the returned struct in a register. This field
00028   // holds the virtual register into which the sret argument is passed.
00029   unsigned SRetReturnReg;
00030   std::vector<MachineInstr*> AllocaAdjustInsts;
00031   int VarArgsFrameIndex;
00032   bool HasClobberLR;
00033   bool HasEHReturn;
00034   std::map<const MachineInstr*, unsigned> PacketInfo;
00035   virtual void anchor();
00036 
00037 public:
00038   HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0),
00039     HasEHReturn(false) {}
00040 
00041   HexagonMachineFunctionInfo(MachineFunction &MF) : SRetReturnReg(0),
00042                                                     HasClobberLR(0),
00043                                                     HasEHReturn(false) {}
00044 
00045   unsigned getSRetReturnReg() const { return SRetReturnReg; }
00046   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
00047 
00048   void addAllocaAdjustInst(MachineInstr* MI) {
00049     AllocaAdjustInsts.push_back(MI);
00050   }
00051   const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
00052     return AllocaAdjustInsts;
00053   }
00054 
00055   void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
00056   int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
00057 
00058   void setStartPacket(MachineInstr* MI) {
00059     PacketInfo[MI] |= Hexagon::StartPacket;
00060   }
00061   void setEndPacket(MachineInstr* MI)   {
00062     PacketInfo[MI] |= Hexagon::EndPacket;
00063   }
00064   bool isStartPacket(const MachineInstr* MI) const {
00065     return (PacketInfo.count(MI) &&
00066             (PacketInfo.find(MI)->second & Hexagon::StartPacket));
00067   }
00068   bool isEndPacket(const MachineInstr* MI) const {
00069     return (PacketInfo.count(MI) &&
00070             (PacketInfo.find(MI)->second & Hexagon::EndPacket));
00071   }
00072   void setHasClobberLR(bool v) { HasClobberLR = v;  }
00073   bool hasClobberLR() const { return HasClobberLR; }
00074 
00075   bool hasEHReturn() const { return HasEHReturn; };
00076   void setHasEHReturn(bool H = true) { HasEHReturn = H; };
00077 };
00078 } // End llvm namespace
00079 
00080 #endif