RedBoot supports the serial port and the built-in ethernet port for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the onboard 8MB flash.
The following RedBoot configurations are supported:
The board manufacturer provides a DOS application which is capable of programming the flash over the PCI bus, and this is required for initial installations of RedBoot. Please see the board manual for information on using this utility. In general, the process involves programming the ROM mode RedBoot image to flash. RedBoot should be programmed to flash address 0x00000000 using the DOS utility.
After booting the initial installation of RedBoot, this warning may be printed:
flash configuration checksum error or invalid key |
RedBoot> fis init
About to initialize [format] FLASH image system - continue (y/n)? y
*** Initialize FLASH Image System
Warning: device contents not erased, some blocks may not be usable
... Unlock from 0xf07e0000-0xf0800000: .
... Erase from 0xf07e0000-0xf0800000: .
... Program from 0x01ddf000-0x01ddf400 at 0xf07e0000: .
... Lock from 0xf07e0000-0xf0800000: . |
The 80321 board is highly configurable through a number of switches and jumpers. RedBoot makes some assumptions about board configuration and attention must be paid to these assumptions for reliable RedBoot operation:
The onboard ethernet and the secondary slot may be placed in a private space so that they are not seen by a PC BIOS. If the board is to be used in a PC with BIOS, then the ethernet should be placed in this private space so that RedBoot and the BIOS do not conflict.
RedBoot assumes that the board is plugged into a PC with BIOS. This requires RedBoot to detect when the BIOS has configured the PCI-X secondary bus. If the board is placed in a backplane, RedBoot will never see the BIOS configure the secondary bus. To prevent this wait, set switch S7E1-3 to ON when using the board in a backplane.
For the remaining switch settings, the following is a known good configuration:
RedBoot uses the two digit LED display to indicate status during board initialization. Possible codes are:
LED Actions
-------------------------------------------------------------
Power-On/Reset
88
Set the CPSR
Enable coprocessor access
Drain write and fill buffer
Setup PBIU chip selects
A1
Enable the Icache
A2
Move FLASH chip select from 0x0 to 0xF0000000
Jump to new FLASH location
A3
Setup and enable the MMU
A4
I2C interface initialization
90
Wait for I2C initialization to complete
91
Send address (via I2C) to the DIMM
92
Wait for transmit complete
93
Read SDRAM PD data from DIMM
94
Read remainder of EEPROM data.
An error will result in one of the following
error codes on the LEDs:
77 BAD EEPROM checksum
55 I2C protocol error
FF bank size error
A5
Setup DDR memory interface
A6
Enable branch target buffer
Drain the write & fill buffers
Flush Icache, Dcache and BTB
Flush instuction and data TLBs
Drain the write & fill buffers
SL
ECC Scrub Loop
SE
A7
Clean, drain, flush the main Dcache
A8
Clean, drain, flush the mini Dcache
Flush Dcache
Drain the write & fill buffers
A9
Enable ECC
AA
Save SDRAM size
Move MMU tables into RAM
AB
Clean, drain, flush the main Dcache
Clean, drain, flush the mini Dcache
Drain the write & fill buffers
AC
Set the TTB register to DRAM mmu_table
AD
Set mode to IRQ mode
A7
Move SWI & Undefined "vectors" to RAM (at 0x0)
A6
Switch to supervisor mode
A5
Move remaining "vectors" to RAM (at 0x0)
A4
Copy DATA to RAM
Initialize interrupt exception environment
Initialize stack
Clear BSS section
A3
Call platform specific hardware initialization
A2
Run through static constructors
A1
Start up the eCos kernel or RedBoot
A special RedBoot command, diag, is used to access a set of hardware diagnostics. To access the diagnostic menu, enter diag at the RedBoot prompt:
RedBoot> diag Entering Hardware Diagnostics - Disabling Data Cache! IQ80321 Hardware Tests 1 - Memory Tests 2 - Repeating Memory Tests 3 - Repeat-On-Fail Memory Tests 4 - Rotary Switch S1 Test 5 - 7 Segment LED Tests 6 - i82544 Ethernet Configuration 7 - Baterry Status Test 8 - Battery Backup SDRAM Memory Test 9 - Timer Test 10 - PCI Bus test 11 - CPU Cache Loop (No Return) 0 - quit Enter the menu item number (0 to quit): |
This test is used to test installed DDR SDRAM memory. Five different tests are run over the given address ranges. If errors are encountered, the test is aborted and information about the failure is printed. When selected, the user will be prompted to enter the base address of the test range and its size. The numbers must be in hex with no leading “0x”
Enter the menu item number (0 to quit): 1 Base address of memory to test (in hex): 100000 Size of memory to test (in hex): 200000 Testing memory from 0x00100000 to 0x002fffff. Walking 1's test: 0000000100000002000000040000000800000010000000200000004000000080 0000010000000200000004000000080000001000000020000000400000008000 0001000000020000000400000008000000100000002000000040000000800000 0100000002000000040000000800000010000000200000004000000080000000 passed 32-bit address test: passed 32-bit address bar test: passed 8-bit address test: passed Byte address bar test: passed Memory test done. |
The repeating memory tests are exactly the same as the above memory tests, except that the tests are automatically rerun after completion. The only way out of this test is to reset the board.
This is similar to the repeating memory tests except that when an error is found, the failing test continuously retries on the failing address.
This tests the operation of the sixteen position rotary switch. When run, this test will display the current position of the rotary switch on the LED display. Slowly dial through each position and confirm reading on LED.
This tests the operation of the seven segment displays. When run, each LED cycles through 0 through F and a decimal point.
This test initializes the ethernet controller’s serial EEPROM if the current contents are invalid. In any case, this test will also allow the user to enter a six byte ethernet MAC address into the serial EEPROM.
Enter the menu item number (0 to quit): 6 Current MAC address: 00:80:4d:46:00:02 Enter desired MAC address: 00:80:4d:46:00:01 Writing to the Serial EEPROM... Done ******** Reset The Board To Have Changes Take Effect ******** |
This tests the current status of the battery. First, the test checks to see if the battery is installed and reports that finding. If the battery is installed, the test further determines whether the battery status is one or more of the following:
Battery is charging.
Battery is fully discharged.
Battery voltage measures within normal operating range.
This tests the battery backup of SDRAM memory. This test is a three step process:
Select Battery backup test from main diag menu, then write data to SDRAM.
Turn off power for 60 seconds, then repower the board.
Select Battery backup test from main diag menu, then check data that was written in step 1.
This tests the internal timer by printing a number of dots at one second intervals.
This tests the secondary PCI-X bus and socket. This test requires that an IQ80310 board be plugged into the secondary slot of the IOP80321 board. The test assumes at least 32MB of installed memory on the IQ80310. That memory is mapped into the IOP80321 address space and the memory tests are run on that memory.
This test puts the CPU into a tight loop run entirely from the ICache. This should prevent all external bus accesses.
These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in Chapter 3:
export TARGET=iq80321 export ARCH_DIR=arm export PLATFORM_DIR=xscale/iq80321 |
The names of configuration files are listed above with the description of the associated modes.
RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype::
int irq_handler( unsigned vector, unsigned data ) |
// *** 80200 CPU *** #define CYGNUM_HAL_INTERRUPT_DMA0_EOT 0 #define CYGNUM_HAL_INTERRUPT_DMA0_EOC 1 #define CYGNUM_HAL_INTERRUPT_DMA1_EOT 2 #define CYGNUM_HAL_INTERRUPT_DMA1_EOC 3 #define CYGNUM_HAL_INTERRUPT_RSVD_4 4 #define CYGNUM_HAL_INTERRUPT_RSVD_5 5 #define CYGNUM_HAL_INTERRUPT_AA_EOT 6 #define CYGNUM_HAL_INTERRUPT_AA_EOC 7 #define CYGNUM_HAL_INTERRUPT_CORE_PMON 8 #define CYGNUM_HAL_INTERRUPT_TIMER0 9 #define CYGNUM_HAL_INTERRUPT_TIMER1 10 #define CYGNUM_HAL_INTERRUPT_I2C_0 11 #define CYGNUM_HAL_INTERRUPT_I2C_1 12 #define CYGNUM_HAL_INTERRUPT_MESSAGING 13 #define CYGNUM_HAL_INTERRUPT_ATU_BIST 14 #define CYGNUM_HAL_INTERRUPT_PERFMON 15 #define CYGNUM_HAL_INTERRUPT_CORE_PMU 16 #define CYGNUM_HAL_INTERRUPT_BIU_ERR 17 #define CYGNUM_HAL_INTERRUPT_ATU_ERR 18 #define CYGNUM_HAL_INTERRUPT_MCU_ERR 19 #define CYGNUM_HAL_INTERRUPT_DMA0_ERR 20 #define CYGNUM_HAL_INTERRUPT_DMA1_ERR 22 #define CYGNUM_HAL_INTERRUPT_AA_ERR 23 #define CYGNUM_HAL_INTERRUPT_MSG_ERR 24 #define CYGNUM_HAL_INTERRUPT_SSP 25 #define CYGNUM_HAL_INTERRUPT_RSVD_26 26 #define CYGNUM_HAL_INTERRUPT_XINT0 27 #define CYGNUM_HAL_INTERRUPT_XINT1 28 #define CYGNUM_HAL_INTERRUPT_XINT2 29 #define CYGNUM_HAL_INTERRUPT_XINT3 30 #define CYGNUM_HAL_INTERRUPT_HPI 31 |
An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot.
The RAM based page table is located at RAM start + 0x4000. RedBoot may be configured for one of two memory maps. The difference between them is the location of RAM and the PCI outbound windows. The alternative memory map may be used when building RedBoot or eCos by using the RAM_ALTMAP and ROM_ALTMAP startup types in the configuration.
NOTE: The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region..
X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid -- not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Physical Address Range Description ----------------------- ---------------------------------- 0x00000000 - 0x7fffffff ATU Outbound Direct Window 0x80000000 - 0x900fffff ATU Outbound Translate Windows 0xa0000000 - 0xbfffffff SDRAM 0xf0000000 - 0xf0800000 FLASH (PBIU CS0) 0xfe800000 - 0xfe800fff UART (PBIU CS1) 0xfe840000 - 0xfe840fff Left 7-segment LED (PBIU CS3) 0xfe850000 - 0xfe850fff Right 7-segment LED (PBIU CS2) 0xfe8d0000 - 0xfe8d0fff Rotary Switch (PBIU CS4) 0xfe8f0000 - 0xfe8f0fff Baterry Status (PBIU CS5) 0xfff00000 - 0xffffffff Verde Memory mapped Registers Default Virtual Map X C B Description ----------------------- - - - ---------------------------------- 0x00000000 - 0x1fffffff 1 1 1 SDRAM 0x20000000 - 0x9fffffff 0 0 0 ATU Outbound Direct Window 0xa0000000 - 0xb00fffff 0 0 0 ATU Outbound Translate Windows 0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM 0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem) 0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0) 0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1) 0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3) 0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2) 0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4) 0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5) 0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers Alternate Virtual Map X C B Description ----------------------- - - - ---------------------------------- 0x00000000 - 0x000fffff 1 1 1 Alias for 1st MB of SDRAM 0x00100000 - 0x7fffffff 0 0 0 ATU Outbound Direct Window 0x80000000 - 0x900fffff 0 0 0 ATU Outbound Translate Windows 0xa0000000 - 0xbfffffff 1 1 1 SDRAM 0xc0000000 - 0xdfffffff 0 0 0 Uncached alias for SDRAM 0xe0000000 - 0xe00fffff 1 1 1 Cache flush region (no phys mem) 0xf0000000 - 0xf0800000 0 1 0 FLASH (PBIU CS0) 0xfe800000 - 0xfe800fff 0 0 0 UART (PBIU CS1) 0xfe840000 - 0xfe840fff 0 0 0 Left 7-segment LED (PBIU CS3) 0xfe850000 - 0xfe850fff 0 0 0 Right 7-segment LED (PBIU CS2) 0xfe8d0000 - 0xfe8d0fff 0 0 0 Rotary Switch (PBIU CS4) 0xfe8f0000 - 0xfe8f0fff 0 0 0 Baterry Status (PBIU CS5) 0xfff00000 - 0xffffffff 0 0 0 Verde Memory mapped Registers |
The Verde programmable timer0 is used for timeout support for networking and XModem file transfers.