OpenRISC
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Introduction
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OpenRISC is an open source hardware RISC CPU design by OpenCores released under the GNU Lesser General Public License. The OpenCores team implemented the design in the verilog hardware description language. Flextronics International and Jennic Ltd. manufactured the OpenRISC as part of an ASIC. Others implemented OpenRISC in a FPGA.
The OpenCores team also ported the GNU toolchain to OpenRISC to support development in several languages. Linux and µClinux have been ported to the processor. Projects: • architecture Research & Definition • openrisc_1200 RISC/DSP Implementation • The GNU Toolchain • architectural_simulator • linux Port & Device Drivers Development • uclinux Port & Device Drivers Development • rtems Port & Device Drivers Development OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As an architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.  Documents• Basic Custom OpenRISC system Software Tutorial v1.0
• OpenRISC 1000 Architecture Manual (2004)
• OpenRISC 1200 RISC/DSP Core Overview
• OpenRISC 1200 IP Core Specification Rev0.7 (2001)
Links• http://www.opencores.org/projects.cgi/web/or1k/ |