A DMA engine on an SBus in a SPARC machine has the following attributes:
Access to addresses ranging from 0xFF000000 to 0xFFFFFFFF only
32-bit DMA counter register
Ability to handle byte-aligned transfers
Support for 1-byte, 2-byte, and 4-byte burst sizes
Minimum effective transfer size of 1 byte
32-bit address register
No scatter-gather list
Operation on sectors only, for example, a disk
A DMA engine on an SBus in a SPARC machine has the following attribute structure:
static ddi_dma_attr_t attributes = { DMA_ATTR_V0, /* Version number */ 0xFF000000, /* low address */ 0xFFFFFFFF, /* high address */ 0xFFFFFFFF, /* counter register max */ 1, /* byte alignment */ 0x7, /* burst sizes: 0x1 | 0x2 | 0x4 */ 0x1, /* minimum transfer size */ 0xFFFFFFFF, /* max transfer size */ 0xFFFFFFFF, /* address register max */ 1, /* no scatter-gather */ 512, /* device operates on sectors */ 0, /* attr flag: set to 0 */ };