This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ecoff format. The default value is 8.

Any mips configuration of as can select big-endian or little-endian output at run time (unlike the other gnu development tools, which must be configured for one or the other). Use -EB to select big-endian output, and -EL for little-endian.

Generate code for a particular MIPS Instruction Set Architecture level. -mips1 corresponds to the r2000 and r3000 processors, -mips2 to the r6000 processor, -mips3 to the r4000 processor, and -mips4 to the r8000 and r10000 processors. -mips5, -mips32, -mips32r2, -mips64, and -mips64r2 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also switch instruction sets during the assembly; see Directives to override the ISA level.

Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.

On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

Assume that 64-bit general purpose registers are available. This is provided in the interests of symmetry with -gp32.

Generate code for the MIPS 16 processor. This is equivalent to putting .set mips16 at the start of the assembly file. -no-mips16 turns off this option.

Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.

Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.

Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.

Insert nops to work around certain VR4120 errata. This option is intended to be used on GCC-generated code: it is not designed to catch all problems in hand-written assembler code.

Generate code for the LSI r4010 chip. This tells the assembler to accept the r4010 specific instructions (addciu, ffc, etc.), and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4010 turns off this option.

Generate code for the MIPS r4650 chip. This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.

For each option -mnnnn, generate code for the MIPS rnnnn chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.

Generate code for a particular MIPS cpu. It is exactly equivalent to -mcpu, except that there are more value of cpu understood. Valid cpu value are:

2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, mips32-4k, sb1

Schedule and tune for a particular MIPS cpu. Valid cpu values are identical to -march=cpu.

Record which ABI the source code uses. The recognized arguments are: 32, n32, o64, 64 and eabi.

This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With gnu as, there is no need for -nocpp, because the gnu assembler itself never runs the C preprocessor.

The -no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers.

By default -construct-floats is selected, allowing construction of these floating point constants.

as automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes as to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

Generate code to take a break exception rather than a trap exception when an error is detected. This is the default.

Control generation of .pdr sections. Off by default on IRIX, on elsewhere.