The PDP-11 version of as has a rich set of machine dependent options.
Generate position-independent (or position-dependent) code.
The default is to generate position-independent code.
These options enables or disables the use of extensions over the base line instruction set as introduced by the first PDP-11 CPU: the KA11. Most options come in two variants: a -mextension that enables extension, and a -mno-extension that disables extension.
The default is to enable all extensions.
Enable all instruction set extensions.
Disable all instruction set extensions.
Enable (or disable) the use of the commercial instruction set, which consists of these instructions: ADDNI, ADDN, ADDPI, ADDP, ASHNI, ASHN, ASHPI, ASHP, CMPCI, CMPC, CMPNI, CMPN, CMPPI, CMPP, CVTLNI, CVTLN, CVTLPI, CVTLP, CVTNLI, CVTNL, CVTNPI, CVTNP, CVTPLI, CVTPL, CVTPNI, CVTPN, DIVPI, DIVP, L2DR, L3DR, LOCCI, LOCC, MATCI, MATC, MOVCI, MOVC, MOVRCI, MOVRC, MOVTCI, MOVTC, MULPI, MULP, SCANCI, SCANC, SKPCI, SKPC, SPANCI, SPANC, SUBNI, SUBN, SUBPI, and SUBP.
Enable (or disable) the use of the CSM instruction.
Enable (or disable) the use of the extended instruction set, which consists of these instructions: ASHC, ASH, DIV, MARK, MUL, RTT, SOB SXT, and XOR.
Enable (or disable) the use of the KEV11 floating-point instructions: FADD, FDIV, FMUL, and FSUB.
Enable (or disable) the use of FP-11 floating-point instructions: ABSF, ADDF, CFCC, CLRF, CMPF, DIVF, LDCFF, LDCIF, LDEXP, LDF, LDFPS, MODF, MULF, NEGF, SETD, SETF, SETI, SETL, STCFF, STCFI, STEXP, STF, STFPS, STST, SUBF, and TSTF.
Enable (or disable) the use of the limited extended instruction set: MARK, RTT, SOB, SXT, and XOR.
The -mno-limited-eis options also implies -mno-eis.
Enable (or disable) the use of the MFPT instruction.
Enable (or disable) the use of multiprocessor instructions: TSTSET and WRTLCK.
Enable (or disable) the use of the MFPS and MTPS instructions.
Enable (or disable) the use of the SPL instruction.
Enable (or disable) the use of the microcode instructions: LDUB, MED, and XFC.
These options enable the instruction set extensions supported by a particular CPU, and disables all other extensions.
KA11 CPU. Base line instruction set only.
KB11 CPU. Enable extended instruction set and SPL.
KD11-A CPU. Enable limited extended instruction set.
KD11-B CPU. Base line instruction set only.
KD11-D CPU. Base line instruction set only.
KD11-E CPU. Enable extended instruction set, MFPS, and MTPS.
KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction set, MFPS, and MTPS.
KD11-K CPU. Enable extended instruction set, LDUB, MED, MFPS, MFPT, MTPS, and XFC.
KD11-Z CPU. Enable extended instruction set, CSM, MFPS, MFPT, MTPS, and SPL.
F11 CPU. Enable extended instruction set, MFPS, MFPT, and MTPS.
J11 CPU. Enable extended instruction set, CSM, MFPS, MFPT, MTPS, SPL, TSTSET, and WRTLCK.
T11 CPU. Enable limited extended instruction set, MFPS, and MTPS.
These options enable the instruction set extensions supported by a particular machine model, and disables all other extensions.
Same as -mkd11f.
Same as -mkd11d.
Same as -mkd11b.
Same as -mka11.
Same as -mt11.
Same as -mf11.
Same as -mkd11e.
Ame as -mkd11e -mfpp.
Same as -mkd11a.
Same as -mkd11z.
Same as -mkb11.
Same as -mj11.
Same as -mkd11k.