The PowerPC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.
The following table lists all available PowerPC options.
Generate code for POWER/2 (RIOS2).
Generate code for POWER (RIOS1)
Generate code for PowerPC 601.
Generate code for PowerPC 603/604.
Generate code for PowerPC 403/405.
Generate code for PowerPC 440. BookE and some 405 instructions.
Generate code for PowerPC 7400/7410/7450/7455.
Generate code for PowerPC 620/625/630.
Generate code for PowerPC 64, including bridge insns.
Generate code for 64-bit BookE.
Generate code for 32-bit BookE.
Generate code for processors with AltiVec instructions.
Generate code for Power4 architecture.
Generate code Power/PowerPC common instructions.
Generate code for any architecture (PWR/PWRX/PPC).
Allow symbolic names for registers.
Do not allow symbolic names for registers.
Support for GCC's -mrelocatble option.
Support for GCC's -mrelocatble-lib option.
Set PPC_EMB bit in ELF flags.
Generate code for a little endian machine.
Generate code for a big endian machine.
Generate code for Solaris.
Do not generate code for Solaris.