clang API Documentation
00001 /*===---- cpuid.h - X86 cpu model detection --------------------------------=== 00002 * 00003 * Permission is hereby granted, free of charge, to any person obtaining a copy 00004 * of this software and associated documentation files (the "Software"), to deal 00005 * in the Software without restriction, including without limitation the rights 00006 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 00007 * copies of the Software, and to permit persons to whom the Software is 00008 * furnished to do so, subject to the following conditions: 00009 * 00010 * The above copyright notice and this permission notice shall be included in 00011 * all copies or substantial portions of the Software. 00012 * 00013 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 00014 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 00015 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 00016 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 00017 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 00018 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 00019 * THE SOFTWARE. 00020 * 00021 *===-----------------------------------------------------------------------=== 00022 */ 00023 00024 #if !(__x86_64__ || __i386__) 00025 #error this header is for x86 only 00026 #endif 00027 00028 /* Responses identification request with %eax 0 */ 00029 /* AMD: "AuthenticAMD" */ 00030 #define signature_AMD_ebx 0x68747541 00031 #define signature_AMD_edx 0x69746e65 00032 #define signature_AMD_ecx 0x444d4163 00033 /* CENTAUR: "CentaurHauls" */ 00034 #define signature_CENTAUR_ebx 0x746e6543 00035 #define signature_CENTAUR_edx 0x48727561 00036 #define signature_CENTAUR_ecx 0x736c7561 00037 /* CYRIX: "CyrixInstead" */ 00038 #define signature_CYRIX_ebx 0x69727943 00039 #define signature_CYRIX_edx 0x736e4978 00040 #define signature_CYRIX_ecx 0x64616574 00041 /* INTEL: "GenuineIntel" */ 00042 #define signature_INTEL_ebx 0x756e6547 00043 #define signature_INTEL_edx 0x49656e69 00044 #define signature_INTEL_ecx 0x6c65746e 00045 /* TM1: "TransmetaCPU" */ 00046 #define signature_TM1_ebx 0x6e617254 00047 #define signature_TM1_edx 0x74656d73 00048 #define signature_TM1_ecx 0x55504361 00049 /* TM2: "GenuineTMx86" */ 00050 #define signature_TM2_ebx 0x756e6547 00051 #define signature_TM2_edx 0x54656e69 00052 #define signature_TM2_ecx 0x3638784d 00053 /* NSC: "Geode by NSC" */ 00054 #define signature_NSC_ebx 0x646f6547 00055 #define signature_NSC_edx 0x43534e20 00056 #define signature_NSC_ecx 0x79622065 00057 /* NEXGEN: "NexGenDriven" */ 00058 #define signature_NEXGEN_ebx 0x4778654e 00059 #define signature_NEXGEN_edx 0x72446e65 00060 #define signature_NEXGEN_ecx 0x6e657669 00061 /* RISE: "RiseRiseRise" */ 00062 #define signature_RISE_ebx 0x65736952 00063 #define signature_RISE_edx 0x65736952 00064 #define signature_RISE_ecx 0x65736952 00065 /* SIS: "SiS SiS SiS " */ 00066 #define signature_SIS_ebx 0x20536953 00067 #define signature_SIS_edx 0x20536953 00068 #define signature_SIS_ecx 0x20536953 00069 /* UMC: "UMC UMC UMC " */ 00070 #define signature_UMC_ebx 0x20434d55 00071 #define signature_UMC_edx 0x20434d55 00072 #define signature_UMC_ecx 0x20434d55 00073 /* VIA: "VIA VIA VIA " */ 00074 #define signature_VIA_ebx 0x20414956 00075 #define signature_VIA_edx 0x20414956 00076 #define signature_VIA_ecx 0x20414956 00077 /* VORTEX: "Vortex86 SoC" */ 00078 #define signature_VORTEX_ebx 0x74726f56 00079 #define signature_VORTEX_edx 0x36387865 00080 #define signature_VORTEX_ecx 0x436f5320 00081 00082 /* Features in %ecx for level 1 */ 00083 #define bit_SSE3 0x00000001 00084 #define bit_PCLMULQDQ 0x00000002 00085 #define bit_DTES64 0x00000004 00086 #define bit_MONITOR 0x00000008 00087 #define bit_DSCPL 0x00000010 00088 #define bit_VMX 0x00000020 00089 #define bit_SMX 0x00000040 00090 #define bit_EIST 0x00000080 00091 #define bit_TM2 0x00000100 00092 #define bit_SSSE3 0x00000200 00093 #define bit_CNXTID 0x00000400 00094 #define bit_FMA 0x00001000 00095 #define bit_CMPXCHG16B 0x00002000 00096 #define bit_xTPR 0x00004000 00097 #define bit_PDCM 0x00008000 00098 #define bit_PCID 0x00020000 00099 #define bit_DCA 0x00040000 00100 #define bit_SSE41 0x00080000 00101 #define bit_SSE42 0x00100000 00102 #define bit_x2APIC 0x00200000 00103 #define bit_MOVBE 0x00400000 00104 #define bit_POPCNT 0x00800000 00105 #define bit_TSCDeadline 0x01000000 00106 #define bit_AESNI 0x02000000 00107 #define bit_XSAVE 0x04000000 00108 #define bit_OSXSAVE 0x08000000 00109 #define bit_AVX 0x10000000 00110 #define bit_RDRND 0x40000000 00111 00112 /* Features in %edx for level 1 */ 00113 #define bit_FPU 0x00000001 00114 #define bit_VME 0x00000002 00115 #define bit_DE 0x00000004 00116 #define bit_PSE 0x00000008 00117 #define bit_TSC 0x00000010 00118 #define bit_MSR 0x00000020 00119 #define bit_PAE 0x00000040 00120 #define bit_MCE 0x00000080 00121 #define bit_CX8 0x00000100 00122 #define bit_APIC 0x00000200 00123 #define bit_SEP 0x00000800 00124 #define bit_MTRR 0x00001000 00125 #define bit_PGE 0x00002000 00126 #define bit_MCA 0x00004000 00127 #define bit_CMOV 0x00008000 00128 #define bit_PAT 0x00010000 00129 #define bit_PSE36 0x00020000 00130 #define bit_PSN 0x00040000 00131 #define bit_CLFSH 0x00080000 00132 #define bit_DS 0x00200000 00133 #define bit_ACPI 0x00400000 00134 #define bit_MMX 0x00800000 00135 #define bit_FXSR 0x01000000 00136 #define bit_FXSAVE bit_FXSR /* for gcc compat */ 00137 #define bit_SSE 0x02000000 00138 #define bit_SSE2 0x04000000 00139 #define bit_SS 0x08000000 00140 #define bit_HTT 0x10000000 00141 #define bit_TM 0x20000000 00142 #define bit_PBE 0x80000000 00143 00144 /* Features in %ebx for level 7 sub-leaf 0 */ 00145 #define bit_FSGSBASE 0x00000001 00146 #define bit_SMEP 0x00000080 00147 #define bit_ENH_MOVSB 0x00000200 00148 00149 #if __i386__ 00150 #define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ 00151 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 00152 : "0"(__level)) 00153 00154 #define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ 00155 __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ 00156 : "0"(__level), "2"(__count)) 00157 #else 00158 /* x86-64 uses %rbx as the base register, so preserve it. */ 00159 #define __cpuid(__level, __eax, __ebx, __ecx, __edx) \ 00160 __asm(" xchgq %%rbx,%q1\n" \ 00161 " cpuid\n" \ 00162 " xchgq %%rbx,%q1" \ 00163 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 00164 : "0"(__level)) 00165 00166 #define __cpuid_count(__level, __count, __eax, __ebx, __ecx, __edx) \ 00167 __asm(" xchgq %%rbx,%q1\n" \ 00168 " cpuid\n" \ 00169 " xchgq %%rbx,%q1" \ 00170 : "=a"(__eax), "=r" (__ebx), "=c"(__ecx), "=d"(__edx) \ 00171 : "0"(__level), "2"(__count)) 00172 #endif 00173 00174 static __inline int __get_cpuid (unsigned int __level, unsigned int *__eax, 00175 unsigned int *__ebx, unsigned int *__ecx, 00176 unsigned int *__edx) { 00177 __cpuid(__level, *__eax, *__ebx, *__ecx, *__edx); 00178 return 1; 00179 } 00180 00181 static __inline int __get_cpuid_max (unsigned int __level, unsigned int *__sig) 00182 { 00183 unsigned int __eax, __ebx, __ecx, __edx; 00184 #if __i386__ 00185 int __cpuid_supported; 00186 00187 __asm(" pushfl\n" 00188 " popl %%eax\n" 00189 " movl %%eax,%%ecx\n" 00190 " xorl $0x00200000,%%eax\n" 00191 " pushl %%eax\n" 00192 " popfl\n" 00193 " pushfl\n" 00194 " popl %%eax\n" 00195 " movl $0,%0\n" 00196 " cmpl %%eax,%%ecx\n" 00197 " je 1f\n" 00198 " movl $1,%0\n" 00199 "1:" 00200 : "=r" (__cpuid_supported) : : "eax", "ecx"); 00201 if (!__cpuid_supported) 00202 return 0; 00203 #endif 00204 00205 __cpuid(__level, __eax, __ebx, __ecx, __edx); 00206 if (__sig) 00207 *__sig = __ebx; 00208 return __eax; 00209 }