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SA-1100.h
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1 /*
2  * FILE SA-1100.h
3  *
4  * Version 1.2
5  * Author Copyright (c) Marc A. Viredaz, 1998
6  * DEC Western Research Laboratory, Palo Alto, CA
7  * Date January 1998 (April 1997)
8  * System StrongARM SA-1100
9  * Language C or ARM Assembly
10  * Purpose Definition of constants related to the StrongARM
11  * SA-1100 microprocessor (Advanced RISC Machine (ARM)
12  * architecture version 4). This file is based on the
13  * StrongARM SA-1100 data sheet version 2.2.
14  *
15  */
16 
17 
18 /* Be sure that virtual mapping is defined right */
19 #ifndef __ASM_ARCH_HARDWARE_H
20 #error You must include hardware.h not SA-1100.h
21 #endif
22 
23 #include "bitfield.h"
24 
25 /*
26  * SA1100 CS line to physical address
27  */
28 
29 #define SA1100_CS0_PHYS 0x00000000
30 #define SA1100_CS1_PHYS 0x08000000
31 #define SA1100_CS2_PHYS 0x10000000
32 #define SA1100_CS3_PHYS 0x18000000
33 #define SA1100_CS4_PHYS 0x40000000
34 #define SA1100_CS5_PHYS 0x48000000
35 
36 /*
37  * Personal Computer Memory Card International Association (PCMCIA) sockets
38  */
39 
40 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
41 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
42 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
43 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
44 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
45 
46 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
47 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
48 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
49 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
50 
51 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
52 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
53 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
54 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
55 
56 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
57  (0x20000000 + (Nb)*PCMCIASp)
58 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
59 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
60  (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
61 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
62  (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
63 
64 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
65 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
66 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
67 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
68 
69 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
70 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
71 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
72 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
73 
74 
75 /*
76  * Universal Serial Bus (USB) Device Controller (UDC) control registers
77  *
78  * Registers
79  * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
80  * Controller (UDC) Control Register (read/write).
81  * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
82  * Controller (UDC) Address Register (read/write).
83  * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
84  * Controller (UDC) Output Maximum Packet size register
85  * (read/write).
86  * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
87  * Controller (UDC) Input Maximum Packet size register
88  * (read/write).
89  * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
90  * Controller (UDC) Control/Status register end-point 0
91  * (read/write).
92  * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
93  * Controller (UDC) Control/Status register end-point 1
94  * (output, read/write).
95  * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
96  * Controller (UDC) Control/Status register end-point 2
97  * (input, read/write).
98  * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
99  * Controller (UDC) Data register end-point 0
100  * (read/write).
101  * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
102  * Controller (UDC) Write Count register end-point 0
103  * (read).
104  * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
105  * Controller (UDC) Data Register (read/write).
106  * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
107  * Controller (UDC) Status Register (read/write).
108  */
109 
110 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
111 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
112 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
113 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
114 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
115 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
116 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
117 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
118 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
119 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
120 #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
121 
122 #define UDCCR_UDD 0x00000001 /* UDC Disable */
123 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
124 #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
125 #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
126  /* (disable) */
127 #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
128  /* (disable) */
129 #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
130  /* (disable) */
131 #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
132  /* (disable) */
133 #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
134 #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
135 
136 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
137 
138 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
139  /* [byte] */
140 #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
141  /* [1..256 byte] */ \
142  (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
143 
144 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
145  /* [byte] */
146 #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
147  /* [1..256 byte] */ \
148  (((Size) - 1) << FShft (UDCIMP_INMAXP))
149 
150 #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
151 #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
152 #define UDCCS0_SST 0x00000004 /* Sent STall */
153 #define UDCCS0_FST 0x00000008 /* Force STall */
154 #define UDCCS0_DE 0x00000010 /* Data End */
155 #define UDCCS0_SE 0x00000020 /* Setup End (read) */
156 #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
157  /* (write) */
158 #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
159 
160 #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
161  /* Service request (read) */
162 #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
163 #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
164 #define UDCCS1_SST 0x00000008 /* Sent STall */
165 #define UDCCS1_FST 0x00000010 /* Force STall */
166 #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
167 
168 #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
169  /* Service request (read) */
170 #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
171 #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
172 #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
173 #define UDCCS2_SST 0x00000010 /* Sent STall */
174 #define UDCCS2_FST 0x00000020 /* Force STall */
175 
176 #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
177 
178 #define UDCWC_WC Fld (4, 0) /* Write Count */
179 
180 #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
181 
182 #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
183 #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
184 #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
185 #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
186 #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
187 #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
188 
189 
190 /*
191  * Universal Asynchronous Receiver/Transmitter (UART) control registers
192  *
193  * Registers
194  * Ser1UTCR0 Serial port 1 Universal Asynchronous
195  * Receiver/Transmitter (UART) Control Register 0
196  * (read/write).
197  * Ser1UTCR1 Serial port 1 Universal Asynchronous
198  * Receiver/Transmitter (UART) Control Register 1
199  * (read/write).
200  * Ser1UTCR2 Serial port 1 Universal Asynchronous
201  * Receiver/Transmitter (UART) Control Register 2
202  * (read/write).
203  * Ser1UTCR3 Serial port 1 Universal Asynchronous
204  * Receiver/Transmitter (UART) Control Register 3
205  * (read/write).
206  * Ser1UTDR Serial port 1 Universal Asynchronous
207  * Receiver/Transmitter (UART) Data Register
208  * (read/write).
209  * Ser1UTSR0 Serial port 1 Universal Asynchronous
210  * Receiver/Transmitter (UART) Status Register 0
211  * (read/write).
212  * Ser1UTSR1 Serial port 1 Universal Asynchronous
213  * Receiver/Transmitter (UART) Status Register 1 (read).
214  *
215  * Ser2UTCR0 Serial port 2 Universal Asynchronous
216  * Receiver/Transmitter (UART) Control Register 0
217  * (read/write).
218  * Ser2UTCR1 Serial port 2 Universal Asynchronous
219  * Receiver/Transmitter (UART) Control Register 1
220  * (read/write).
221  * Ser2UTCR2 Serial port 2 Universal Asynchronous
222  * Receiver/Transmitter (UART) Control Register 2
223  * (read/write).
224  * Ser2UTCR3 Serial port 2 Universal Asynchronous
225  * Receiver/Transmitter (UART) Control Register 3
226  * (read/write).
227  * Ser2UTCR4 Serial port 2 Universal Asynchronous
228  * Receiver/Transmitter (UART) Control Register 4
229  * (read/write).
230  * Ser2UTDR Serial port 2 Universal Asynchronous
231  * Receiver/Transmitter (UART) Data Register
232  * (read/write).
233  * Ser2UTSR0 Serial port 2 Universal Asynchronous
234  * Receiver/Transmitter (UART) Status Register 0
235  * (read/write).
236  * Ser2UTSR1 Serial port 2 Universal Asynchronous
237  * Receiver/Transmitter (UART) Status Register 1 (read).
238  *
239  * Ser3UTCR0 Serial port 3 Universal Asynchronous
240  * Receiver/Transmitter (UART) Control Register 0
241  * (read/write).
242  * Ser3UTCR1 Serial port 3 Universal Asynchronous
243  * Receiver/Transmitter (UART) Control Register 1
244  * (read/write).
245  * Ser3UTCR2 Serial port 3 Universal Asynchronous
246  * Receiver/Transmitter (UART) Control Register 2
247  * (read/write).
248  * Ser3UTCR3 Serial port 3 Universal Asynchronous
249  * Receiver/Transmitter (UART) Control Register 3
250  * (read/write).
251  * Ser3UTDR Serial port 3 Universal Asynchronous
252  * Receiver/Transmitter (UART) Data Register
253  * (read/write).
254  * Ser3UTSR0 Serial port 3 Universal Asynchronous
255  * Receiver/Transmitter (UART) Status Register 0
256  * (read/write).
257  * Ser3UTSR1 Serial port 3 Universal Asynchronous
258  * Receiver/Transmitter (UART) Status Register 1 (read).
259  *
260  * Clocks
261  * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
262  * or 3.5795 MHz).
263  * fua, Tua Frequency, period of the UART communication.
264  */
265 
266 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
267 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
268 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
269 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
270 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
271 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
272 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
273 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
274 
275 #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
276 #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
277 #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
278 #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
279 #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
280 #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
281 #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
282 
283 #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
284 #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
285 #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
286 #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
287 #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
288 #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
289 #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
290 #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
291 
292 #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
293 #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
294 #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
295 #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
296 #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
297 #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
298 #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
299 
300 /* Those are still used in some places */
301 #define _Ser1UTCR0 __PREG(Ser1UTCR0)
302 #define _Ser2UTCR0 __PREG(Ser2UTCR0)
303 #define _Ser3UTCR0 __PREG(Ser3UTCR0)
304 
305 /* Register offsets */
306 #define UTCR0 0x00
307 #define UTCR1 0x04
308 #define UTCR2 0x08
309 #define UTCR3 0x0c
310 #define UTDR 0x14
311 #define UTSR0 0x1c
312 #define UTSR1 0x20
313 
314 #define UTCR0_PE 0x00000001 /* Parity Enable */
315 #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
316 #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
317 #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
318 #define UTCR0_SBS 0x00000004 /* Stop Bit Select */
319 #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
320 #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
321 #define UTCR0_DSS 0x00000008 /* Data Size Select */
322 #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
323 #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
324 #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
325  /* (ser. port 1: GPIO [18], */
326  /* ser. port 3: GPIO [20]) */
327 #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
328 #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
329 #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
330 #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
331 #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
332 #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
333 #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
334  (UTCR0_1StpBit + UTCR0_8BitData)
335 
336 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
337 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
338  /* fua = fxtl/(16*(BRD[11:0] + 1)) */
339  /* Tua = 16*(BRD [11:0] + 1)*Txtl */
340 #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
341  (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
342  FShft (UTCR1_BRD))
343 #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
344  (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
345  FShft (UTCR2_BRD))
346  /* fua = fxtl/(16*Floor (Div/16)) */
347  /* Tua = 16*Floor (Div/16)*Txtl */
348 #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
349  (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
350  FShft (UTCR1_BRD))
351 #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
352  (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
353  FShft (UTCR2_BRD))
354  /* fua = fxtl/(16*Ceil (Div/16)) */
355  /* Tua = 16*Ceil (Div/16)*Txtl */
356 
357 #define UTCR3_RXE 0x00000001 /* Receive Enable */
358 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
359 #define UTCR3_BRK 0x00000004 /* BReaK mode */
360 #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
361  /* more Interrupt Enable */
362 #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
363  /* Interrupt Enable */
364 #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
365 #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
366  /* TIE, LBM can be set or cleared) */ \
367  (UTCR3_RXE + UTCR3_TXE)
368 
369 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
370  /* (HP-SIR) modulation Enable */
371 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
372 #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
373 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
374 #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
375 #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
376 
377 #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
378 #if 0 /* Hidden receive FIFO bits */
379 #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
380 #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
381 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
382 #endif /* 0 */
383 
384 #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
385  /* Service request (read) */
386 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
387  /* more Service request (read) */
388 #define UTSR0_RID 0x00000004 /* Receiver IDle */
389 #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
390 #define UTSR0_REB 0x00000010 /* Receive End of Break */
391 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
392 
393 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
394 #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
395 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
396 #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
397 #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
398 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
399 
400 
401 /*
402  * Synchronous Data Link Controller (SDLC) control registers
403  *
404  * Registers
405  * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
406  * Control Register 0 (read/write).
407  * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
408  * Control Register 1 (read/write).
409  * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
410  * Control Register 2 (read/write).
411  * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
412  * Control Register 3 (read/write).
413  * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
414  * Control Register 4 (read/write).
415  * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
416  * Data Register (read/write).
417  * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
418  * Status Register 0 (read/write).
419  * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
420  * Status Register 1 (read/write).
421  *
422  * Clocks
423  * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
424  * or 3.5795 MHz).
425  * fsd, Tsd Frequency, period of the SDLC communication.
426  */
427 
428 #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
429 #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
430 #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
431 #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
432 #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
433 #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
434 #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
435 #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
436 
437 #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
438 #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
439 #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
440 #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
441 #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
442 #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
443 #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
444 #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
445 #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
446 #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
447 #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
448 #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
449  /* (GPIO [16]) */
450 #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
451 #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
452 #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
453 #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
454 #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
455 #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
456 #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
457 #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
458 
459 #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
460  /* (GPIO [17]) */
461 #define SDCR1_TXE 0x00000002 /* Transmit Enable */
462 #define SDCR1_RXE 0x00000004 /* Receive Enable */
463 #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
464  /* more Interrupt Enable */
465 #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
466  /* Interrupt Enable */
467 #define SDCR1_AME 0x00000020 /* Address Match Enable */
468 #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
469 #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
470 #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
471 #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
472 
473 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
474 
475 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
476 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
477  /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
478  /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
479 #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
480  (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
481  FShft (SDCR3_BRD))
482 #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
483  (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
484  FShft (SDCR4_BRD))
485  /* fsd = fxtl/(16*Floor (Div/16)) */
486  /* Tsd = 16*Floor (Div/16)*Txtl */
487 #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
488  (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
489  FShft (SDCR3_BRD))
490 #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
491  (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
492  FShft (SDCR4_BRD))
493  /* fsd = fxtl/(16*Ceil (Div/16)) */
494  /* Tsd = 16*Ceil (Div/16)*Txtl */
495 
496 #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
497 #if 0 /* Hidden receive FIFO bits */
498 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
499 #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
500 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
501 #endif /* 0 */
502 
503 #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
504 #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
505 #define SDSR0_RAB 0x00000004 /* Receive ABort */
506 #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
507  /* Service request (read) */
508 #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
509  /* more Service request (read) */
510 
511 #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
512 #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
513 #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
514 #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
515 #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
516 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
517 #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
518 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
519 
520 
521 /*
522  * High-Speed Serial to Parallel controller (HSSP) control registers
523  *
524  * Registers
525  * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
526  * controller (HSSP) Control Register 0 (read/write).
527  * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
528  * controller (HSSP) Control Register 1 (read/write).
529  * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
530  * controller (HSSP) Data Register (read/write).
531  * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
532  * controller (HSSP) Status Register 0 (read/write).
533  * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
534  * controller (HSSP) Status Register 1 (read).
535  * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
536  * controller (HSSP) Control Register 2 (read/write).
537  * [The HSCR2 register is only implemented in
538  * versions 2.0 (rev. = 8) and higher of the StrongARM
539  * SA-1100.]
540  */
541 
542 #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
543 #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
544 #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
545 #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
546 #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
547 #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
548 
549 #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
550 #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
551 #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
552 #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
553 #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
554 #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
555 #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
556 #define HSCR0_TXE 0x00000008 /* Transmit Enable */
557 #define HSCR0_RXE 0x00000010 /* Receive Enable */
558 #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
559  /* more Interrupt Enable */
560 #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
561  /* Interrupt Enable */
562 #define HSCR0_AME 0x00000080 /* Address Match Enable */
563 
564 #define HSCR1_AMV Fld (8, 0) /* Address Match Value */
565 
566 #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
567 #if 0 /* Hidden receive FIFO bits */
568 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
569 #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
570 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
571 #endif /* 0 */
572 
573 #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
574 #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
575 #define HSSR0_RAB 0x00000004 /* Receive ABort */
576 #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
577  /* Service request (read) */
578 #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
579  /* more Service request (read) */
580 #define HSSR0_FRE 0x00000020 /* receive FRaming Error */
581 
582 #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
583 #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
584 #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
585 #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
586 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
587 #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
588 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
589 
590 #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
591 #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
592  /* (inverted) */
593 #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
594  /* (non-inverted) */
595 #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
596 #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
597  /* (inverted) */
598 #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
599  /* (non-inverted) */
600 
601 
602 /*
603  * Multi-media Communications Port (MCP) control registers
604  *
605  * Registers
606  * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
607  * Control Register 0 (read/write).
608  * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
609  * Data Register 0 (audio, read/write).
610  * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
611  * Data Register 1 (telecom, read/write).
612  * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
613  * Data Register 2 (CODEC registers, read/write).
614  * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
615  * Status Register (read/write).
616  * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
617  * Control Register 1 (read/write).
618  * [The MCCR1 register is only implemented in
619  * versions 2.0 (rev. = 8) and higher of the StrongARM
620  * SA-1100.]
621  *
622  * Clocks
623  * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
624  * 12 MHz, or GPIO [21]).
625  * faud, Taud Frequency, period of the audio sampling.
626  * ftcm, Ttcm Frequency, period of the telecom sampling.
627  */
628 
629 #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
630 #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
631 #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
632 #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
633 #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
634 #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
635 
636 #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
637  /* [6..127] */
638  /* faud = fmc/(32*ASD) */
639  /* Taud = 32*ASD*Tmc */
640 #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
641  /* [192..4064] */ \
642  ((Div)/32 << FShft (MCCR0_ASD))
643  /* faud = fmc/(32*Floor (Div/32)) */
644  /* Taud = 32*Floor (Div/32)*Tmc */
645 #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
646  (((Div) + 31)/32 << FShft (MCCR0_ASD))
647  /* faud = fmc/(32*Ceil (Div/32)) */
648  /* Taud = 32*Ceil (Div/32)*Tmc */
649 #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
650  /* Divisor/32 [16..127] */
651  /* ftcm = fmc/(32*TSD) */
652  /* Ttcm = 32*TSD*Tmc */
653 #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
654  /* [512..4064] */ \
655  ((Div)/32 << FShft (MCCR0_TSD))
656  /* ftcm = fmc/(32*Floor (Div/32)) */
657  /* Ttcm = 32*Floor (Div/32)*Tmc */
658 #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
659  (((Div) + 31)/32 << FShft (MCCR0_TSD))
660  /* ftcm = fmc/(32*Ceil (Div/32)) */
661  /* Ttcm = 32*Ceil (Div/32)*Tmc */
662 #define MCCR0_MCE 0x00010000 /* MCP Enable */
663 #define MCCR0_ECS 0x00020000 /* External Clock Select */
664 #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
665 #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
666 #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
667  /* sampling/storing Mode */
668 #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
669 #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
670 #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
671  /* or less interrupt Enable */
672 #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
673  /* or more interrupt Enable */
674 #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
675  /* or less interrupt Enable */
676 #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
677  /* more interrupt Enable */
678 #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
679 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
680 #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
681  (((Div) - 1) << FShft (MCCR0_ECP))
682 
683 #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
684  /* FIFOs */
685 
686 #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
687  /* FIFOs */
688 
689  /* receive/transmit CODEC reg. */
690  /* FIFOs: */
691 #define MCDR2_DATA Fld (16, 0) /* reg. DATA */
692 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
693 #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
694 #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
695 #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
696 
697 #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
698  /* or less Service request (read) */
699 #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
700  /* more Service request (read) */
701 #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
702  /* or less Service request (read) */
703 #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
704  /* or more Service request (read) */
705 #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
706 #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
707 #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
708 #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
709 #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
710  /* (read) */
711 #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
712  /* (read) */
713 #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
714  /* (read) */
715 #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
716  /* (read) */
717 #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
718  /* (read) */
719 #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
720  /* (read) */
721 #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
722 #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
723 
724 #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
725 #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
726  /* (11.981 MHz) */
727 #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
728  /* (9.585 MHz) */
729 
730 
731 /*
732  * Synchronous Serial Port (SSP) control registers
733  *
734  * Registers
735  * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
736  * Register 0 (read/write).
737  * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
738  * Register 1 (read/write).
739  * [Bits SPO and SP are only implemented in versions 2.0
740  * (rev. = 8) and higher of the StrongARM SA-1100.]
741  * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
742  * Register (read/write).
743  * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
744  * Register (read/write).
745  *
746  * Clocks
747  * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
748  * or 3.5795 MHz).
749  * fss, Tss Frequency, period of the SSP communication.
750  */
751 
752 #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
753 #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
754 #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
755 #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
756 
757 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
758 #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
759  (((Size) - 1) << FShft (SSCR0_DSS))
760 #define SSCR0_FRF Fld (2, 4) /* FRame Format */
761 #define SSCR0_Motorola /* Motorola Serial Peripheral */ \
762  /* Interface (SPI) format */ \
763  (0 << FShft (SSCR0_FRF))
764 #define SSCR0_TI /* Texas Instruments Synchronous */ \
765  /* Serial format */ \
766  (1 << FShft (SSCR0_FRF))
767 #define SSCR0_National /* National Microwire format */ \
768  (2 << FShft (SSCR0_FRF))
769 #define SSCR0_SSE 0x00000080 /* SSP Enable */
770 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
771  /* fss = fxtl/(2*(SCR + 1)) */
772  /* Tss = 2*(SCR + 1)*Txtl */
773 #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
774  (((Div) - 2)/2 << FShft (SSCR0_SCR))
775  /* fss = fxtl/(2*Floor (Div/2)) */
776  /* Tss = 2*Floor (Div/2)*Txtl */
777 #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
778  (((Div) - 1)/2 << FShft (SSCR0_SCR))
779  /* fss = fxtl/(2*Ceil (Div/2)) */
780  /* Tss = 2*Ceil (Div/2)*Txtl */
781 
782 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
783  /* Interrupt Enable */
784 #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
785  /* Interrupt Enable */
786 #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
787 #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
788 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
789 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
790 #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
791 #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
792  /* after frame (SFRM, 1st edge) */
793 #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
794  /* after frame (SFRM, 1st edge) */
795 #define SSCR1_ECS 0x00000020 /* External Clock Select */
796 #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
797 #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
798 
799 #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
800 
801 #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
802 #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
803 #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
804 #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
805  /* Service request (read) */
806 #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
807  /* Service request (read) */
808 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
809 
810 
811 /*
812  * Operating System (OS) timer control registers
813  *
814  * Registers
815  * OSMR0 Operating System (OS) timer Match Register 0
816  * (read/write).
817  * OSMR1 Operating System (OS) timer Match Register 1
818  * (read/write).
819  * OSMR2 Operating System (OS) timer Match Register 2
820  * (read/write).
821  * OSMR3 Operating System (OS) timer Match Register 3
822  * (read/write).
823  * OSCR Operating System (OS) timer Counter Register
824  * (read/write).
825  * OSSR Operating System (OS) timer Status Register
826  * (read/write).
827  * OWER Operating System (OS) timer Watch-dog Enable Register
828  * (read/write).
829  * OIER Operating System (OS) timer Interrupt Enable Register
830  * (read/write).
831  */
832 
833 #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */
834 #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
835 #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */
836 #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */
837 #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */
838 #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */
839 #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
840 #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
841 
842 #define OSSR_M(Nb) /* Match detected [0..3] */ \
843  (0x00000001 << (Nb))
844 #define OSSR_M0 OSSR_M (0) /* Match detected 0 */
845 #define OSSR_M1 OSSR_M (1) /* Match detected 1 */
846 #define OSSR_M2 OSSR_M (2) /* Match detected 2 */
847 #define OSSR_M3 OSSR_M (3) /* Match detected 3 */
848 
849 #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
850  /* (set only) */
851 
852 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
853  (0x00000001 << (Nb))
854 #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
855 #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
856 #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
857 #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
858 
859 
860 /*
861  * Real-Time Clock (RTC) control registers
862  *
863  * Registers
864  * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
865  * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
866  * RTTR Real-Time Clock (RTC) Trim Register (read/write).
867  * RTSR Real-Time Clock (RTC) Status Register (read/write).
868  *
869  * Clocks
870  * frtx, Trtx Frequency, period of the real-time clock crystal
871  * (32.768 kHz nominal).
872  * frtc, Trtc Frequency, period of the real-time clock counter
873  * (1 Hz nominal).
874  */
875 
876 #define RTAR __REG(0x90010000) /* RTC Alarm Reg. */
877 #define RCNR __REG(0x90010004) /* RTC CouNt Reg. */
878 #define RTTR __REG(0x90010008) /* RTC Trim Reg. */
879 #define RTSR __REG(0x90010010) /* RTC Status Reg. */
880 
881 #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
882 #define RTTR_D Fld (10, 16) /* trim Delete count */
883  /* frtc = (1023*(C + 1) - D)*frtx/ */
884  /* (1023*(C + 1)^2) */
885  /* Trtc = (1023*(C + 1)^2)*Trtx/ */
886  /* (1023*(C + 1) - D) */
887 
888 #define RTSR_AL 0x00000001 /* ALarm detected */
889 #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
890 #define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
891 #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
892 
893 
894 /*
895  * Power Manager (PM) control registers
896  *
897  * Registers
898  * PMCR Power Manager (PM) Control Register (read/write).
899  * PSSR Power Manager (PM) Sleep Status Register (read/write).
900  * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
901  * PWER Power Manager (PM) Wake-up Enable Register
902  * (read/write).
903  * PCFR Power Manager (PM) general ConFiguration Register
904  * (read/write).
905  * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
906  * Configuration Register (read/write).
907  * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
908  * Sleep state Register (read/write, see GPIO pins).
909  * POSR Power Manager (PM) Oscillator Status Register (read).
910  *
911  * Clocks
912  * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
913  * or 3.5795 MHz).
914  * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
915  */
916 
917 #define PMCR __REG(0x90020000) /* PM Control Reg. */
918 #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
919 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
920 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
921 #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
922 #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
923 #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
924 #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
925 
926 #define PMCR_SF 0x00000001 /* Sleep Force (set only) */
927 
928 #define PSSR_SS 0x00000001 /* Software Sleep */
929 #define PSSR_BFS 0x00000002 /* Battery Fault Status */
930  /* (BATT_FAULT) */
931 #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
932 #define PSSR_DH 0x00000008 /* DRAM control Hold */
933 #define PSSR_PH 0x00000010 /* Peripheral control Hold */
934 
935 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
936 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
937 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
938 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
939 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
940 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
941 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
942 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
943 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
944 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
945 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
946 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
947 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
948 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
949 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
950 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
951 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
952 #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
953 #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
954 #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
955 #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
956 #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
957 #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
958 #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
959 #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
960 #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
961 #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
962 #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
963 #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
964 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
965 
966 #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
967 #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
968 #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
969 #define PCFR_FP 0x00000002 /* Float PCMCIA pins */
970 #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
971 #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
972 #define PCFR_FS 0x00000004 /* Float Static memory pins */
973 #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
974 #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
975 #define PCFR_FO 0x00000008 /* Force RTC oscillator */
976  /* (32.768 kHz) enable On */
977 
978 #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
979 #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
980  (0x00 << FShft (PPCR_CCF))
981 #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
982  (0x01 << FShft (PPCR_CCF))
983 #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
984  (0x02 << FShft (PPCR_CCF))
985 #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
986  (0x03 << FShft (PPCR_CCF))
987 #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
988  (0x04 << FShft (PPCR_CCF))
989 #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
990  (0x05 << FShft (PPCR_CCF))
991 #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
992  (0x06 << FShft (PPCR_CCF))
993 #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
994  (0x07 << FShft (PPCR_CCF))
995 #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
996  (0x08 << FShft (PPCR_CCF))
997 #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
998  (0x09 << FShft (PPCR_CCF))
999 #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
1000  (0x0A << FShft (PPCR_CCF))
1001 #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
1002  (0x0B << FShft (PPCR_CCF))
1003 #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
1004  (0x0C << FShft (PPCR_CCF))
1005 #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
1006  (0x0D << FShft (PPCR_CCF))
1007 #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
1008  (0x0E << FShft (PPCR_CCF))
1009 #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
1010  (0x0F << FShft (PPCR_CCF))
1011  /* 3.6864 MHz crystal (fxtl): */
1012 #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
1013 #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
1014 #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
1015 #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
1016 #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
1017 #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
1018 #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
1019 #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
1020 #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
1021 #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
1022 #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
1023 #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
1024 #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
1025 #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
1026 #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
1027 #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
1028  /* 3.5795 MHz crystal (fxtl): */
1029 #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
1030 #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
1031 #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
1032 #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
1033 #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
1034 #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
1035 #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
1036 #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
1037 #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
1038 #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
1039 #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
1040 #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
1041 #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
1042 #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
1043 #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
1044 #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
1045 
1046 #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
1047 
1048 
1049 /*
1050  * Reset Controller (RC) control registers
1051  *
1052  * Registers
1053  * RSRR Reset Controller (RC) Software Reset Register
1054  * (read/write).
1055  * RCSR Reset Controller (RC) Status Register (read/write).
1056  */
1057 
1058 #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
1059 #define RCSR __REG(0x90030004) /* RC Status Reg. */
1060 
1061 #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
1062 
1063 #define RCSR_HWR 0x00000001 /* HardWare Reset */
1064 #define RCSR_SWR 0x00000002 /* SoftWare Reset */
1065 #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1066 #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1067 
1068 
1069 /*
1070  * Test unit control registers
1071  *
1072  * Registers
1073  * TUCR Test Unit Control Register (read/write).
1074  */
1075 
1076 #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
1077 
1078 #define TUCR_TIC 0x00000040 /* TIC mode */
1079 #define TUCR_TTST 0x00000080 /* Trim TeST mode */
1080 #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
1081  /* Check */
1082 #define TUCR_PMD 0x00000200 /* Power Management Disable */
1083 #define TUCR_MR 0x00000400 /* Memory Request mode */
1084 #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
1085 #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
1086  /* grant (MBGNT) on GPIO [22:21] */
1087 #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
1088 #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
1089 #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
1090 #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
1091 #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
1092 #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
1093 #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
1094  (0 << FShft (TUCR_TSEL))
1095 #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
1096  (1 << FShft (TUCR_TSEL))
1097 #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
1098  (2 << FShft (TUCR_TSEL))
1099 #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
1100  (3 << FShft (TUCR_TSEL))
1101 #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
1102  /* Clocks on GPIO [26:27] */ \
1103  (4 << FShft (TUCR_TSEL))
1104 #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
1105  /* (Alternative) */ \
1106  (5 << FShft (TUCR_TSEL))
1107 #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
1108  (6 << FShft (TUCR_TSEL))
1109 #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
1110  (7 << FShft (TUCR_TSEL))
1111 
1112 
1113 /*
1114  * General-Purpose Input/Output (GPIO) control registers
1115  *
1116  * Registers
1117  * GPLR General-Purpose Input/Output (GPIO) Pin Level
1118  * Register (read).
1119  * GPDR General-Purpose Input/Output (GPIO) Pin Direction
1120  * Register (read/write).
1121  * GPSR General-Purpose Input/Output (GPIO) Pin output Set
1122  * Register (write).
1123  * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
1124  * Register (write).
1125  * GRER General-Purpose Input/Output (GPIO) Rising-Edge
1126  * detect Register (read/write).
1127  * GFER General-Purpose Input/Output (GPIO) Falling-Edge
1128  * detect Register (read/write).
1129  * GEDR General-Purpose Input/Output (GPIO) Edge Detect
1130  * status Register (read/write).
1131  * GAFR General-Purpose Input/Output (GPIO) Alternate
1132  * Function Register (read/write).
1133  *
1134  * Clock
1135  * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1136  */
1137 
1138 #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
1139 #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
1140 #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
1141 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
1142 #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
1143 #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
1144 #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
1145 #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
1146 
1147 #define GPIO_MIN (0)
1148 #define GPIO_MAX (27)
1149 
1150 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
1151  (0x00000001 << (Nb))
1152 #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
1153 #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
1154 #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
1155 #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
1156 #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
1157 #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
1158 #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
1159 #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
1160 #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
1161 #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
1162 #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
1163 #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
1164 #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
1165 #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
1166 #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
1167 #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
1168 #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
1169 #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
1170 #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
1171 #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
1172 #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
1173 #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
1174 #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
1175 #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
1176 #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
1177 #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
1178 #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
1179 #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
1180 
1181 #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
1182  GPIO_GPIO ((Nb) - 6)
1183 #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
1184 #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
1185 #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
1186 #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
1187 #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
1188 #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
1189 #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
1190 #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
1191  /* ser. port 4: */
1192 #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
1193 #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
1194 #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
1195 #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
1196  /* ser. port 1: */
1197 #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
1198 #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
1199 #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
1200 #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
1201 #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
1202  /* ser. port 4: */
1203 #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
1204  /* ser. port 3: */
1205 #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
1206  /* ser. port 4: */
1207 #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
1208  /* test controller: */
1209 #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
1210 #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
1211 #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
1212 #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
1213 #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
1214 #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
1215 #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
1216 #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
1217 
1218 #define GPDR_In 0 /* Input */
1219 #define GPDR_Out 1 /* Output */
1220 
1221 
1222 /*
1223  * Interrupt Controller (IC) control registers
1224  *
1225  * Registers
1226  * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
1227  * Pending register (read).
1228  * ICMR Interrupt Controller (IC) Mask Register (read/write).
1229  * ICLR Interrupt Controller (IC) Level Register (read/write).
1230  * ICCR Interrupt Controller (IC) Control Register
1231  * (read/write).
1232  * [The ICCR register is only implemented in versions 2.0
1233  * (rev. = 8) and higher of the StrongARM SA-1100.]
1234  * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
1235  * (FIQ) Pending register (read).
1236  * ICPR Interrupt Controller (IC) Pending Register (read).
1237  * [The ICPR register is active low (inverted) in
1238  * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1239  * StrongARM SA-1100, it is active high (non-inverted) in
1240  * versions 2.0 (rev. = 8) and higher.]
1241  */
1242 
1243 #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
1244 #define ICMR __REG(0x90050004) /* IC Mask Reg. */
1245 #define ICLR __REG(0x90050008) /* IC Level Reg. */
1246 #define ICCR __REG(0x9005000C) /* IC Control Reg. */
1247 #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
1248 #define ICPR __REG(0x90050020) /* IC Pending Reg. */
1249 
1250 #define IC_GPIO(Nb) /* GPIO [0..10] */ \
1251  (0x00000001 << (Nb))
1252 #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
1253 #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
1254 #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
1255 #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
1256 #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
1257 #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
1258 #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
1259 #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
1260 #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
1261 #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
1262 #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
1263 #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
1264 #define IC_LCD 0x00001000 /* LCD controller */
1265 #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
1266 #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
1267 #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
1268 #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
1269 #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
1270 #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
1271 #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
1272 #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
1273  (0x00100000 << (Nb))
1274 #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
1275 #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
1276 #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
1277 #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
1278 #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
1279 #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
1280 #define IC_OST(Nb) /* OS Timer match [0..3] */ \
1281  (0x04000000 << (Nb))
1282 #define IC_OST0 IC_OST (0) /* OS Timer match 0 */
1283 #define IC_OST1 IC_OST (1) /* OS Timer match 1 */
1284 #define IC_OST2 IC_OST (2) /* OS Timer match 2 */
1285 #define IC_OST3 IC_OST (3) /* OS Timer match 3 */
1286 #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
1287 #define IC_RTCAlrm 0x80000000 /* RTC Alarm */
1288 
1289 #define ICLR_IRQ 0 /* Interrupt ReQuest */
1290 #define ICLR_FIQ 1 /* Fast Interrupt reQuest */
1291 
1292 #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1293  /* Mask */
1294 #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1295  /* (ICMR ignored) */
1296 #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
1297  /* enable (ICMR used) */
1298 
1299 
1300 /*
1301  * Peripheral Pin Controller (PPC) control registers
1302  *
1303  * Registers
1304  * PPDR Peripheral Pin Controller (PPC) Pin Direction
1305  * Register (read/write).
1306  * PPSR Peripheral Pin Controller (PPC) Pin State Register
1307  * (read/write).
1308  * PPAR Peripheral Pin Controller (PPC) Pin Assignment
1309  * Register (read/write).
1310  * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
1311  * Direction Register (read/write).
1312  * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
1313  * (read).
1314  */
1315 
1316 #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
1317 #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
1318 #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
1319 #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
1320 #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
1321 
1322 #define PPC_LDD(Nb) /* LCD Data [0..7] */ \
1323  (0x00000001 << (Nb))
1324 #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
1325 #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
1326 #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
1327 #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
1328 #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
1329 #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
1330 #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
1331 #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
1332 #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
1333 #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
1334 #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
1335 #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
1336  /* ser. port 1: */
1337 #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
1338 #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
1339  /* ser. port 2: */
1340 #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
1341 #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
1342  /* ser. port 3: */
1343 #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
1344 #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
1345  /* ser. port 4: */
1346 #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
1347 #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
1348 #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
1349 #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
1350 
1351 #define PPDR_In 0 /* Input */
1352 #define PPDR_Out 1 /* Output */
1353 
1354  /* ser. port 1: */
1355 #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
1356 #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
1357 #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
1358  /* ser. port 4: */
1359 #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
1360 #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
1361  /* & SFRM_C */
1362 #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
1363 
1364 #define PSDR_OutL 0 /* Output Low in sleep mode */
1365 #define PSDR_Flt 1 /* Floating (input) in sleep mode */
1366 
1367 #define PPFR_LCD 0x00000001 /* LCD controller */
1368 #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
1369 #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
1370 #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
1371 #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
1372 #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
1373 #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
1374 #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
1375 #define PPFR_PerEn 0 /* Peripheral Enabled */
1376 #define PPFR_PPCEn 1 /* PPC Enabled */
1377 
1378 
1379 /*
1380  * Dynamic Random-Access Memory (DRAM) control registers
1381  *
1382  * Registers
1383  * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1384  * CoNFiGuration register (read/write).
1385  * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1386  * Column Address Strobe (CAS) shift register 0
1387  * (read/write).
1388  * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1389  * Column Address Strobe (CAS) shift register 1
1390  * (read/write).
1391  * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1392  * Column Address Strobe (CAS) shift register 2
1393  * (read/write).
1394  *
1395  * Clocks
1396  * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1397  * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1398  * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
1399  */
1400 
1401 #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
1402 #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
1403 #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
1404 #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
1405 
1406 /* SA1100 MDCNFG values */
1407 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
1408  (0x00000001 << (Nb))
1409 #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
1410 #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
1411 #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
1412 #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
1413 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1414 #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
1415  (((Add) - 9) << FShft (MDCNFG_DRAC))
1416 #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
1417  /* (fcas = fcpu/2) */
1418 #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1419 #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
1420  (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1421 #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
1422  (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1423 #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1424 #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
1425  (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1426 #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
1427  (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1428 #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
1429 #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
1430  ((Tcpu) << FShft (MDCNFG_TDL))
1431 #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
1432  /* [Tmem] */
1433 #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
1434  /* [0..262136 Tcpu] */ \
1435  ((Tcpu)/8 << FShft (MDCNFG_DRI))
1436 
1437 /* SA1110 MDCNFG values */
1438 #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
1439 #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
1440 #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
1441 #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
1442 #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
1443  /* bank 0/1 */
1444 #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
1445 #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
1446 #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
1447  /* deassertion 0/1 */
1448 #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1449 #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
1450 #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
1451 #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
1452 #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
1453 #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
1454  /* bank 0/1 */
1455 #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
1456 #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
1457 #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
1458  /* deassertion 0/1 */
1459 #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1460 
1461 
1462 /*
1463  * Static memory control registers
1464  *
1465  * Registers
1466  * MSC0 Memory system: Static memory Control register 0
1467  * (read/write).
1468  * MSC1 Memory system: Static memory Control register 1
1469  * (read/write).
1470  *
1471  * Clocks
1472  * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1473  * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1474  */
1475 
1476 #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
1477 #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
1478 #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
1479 
1480 #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
1481  Fld (16, ((Nb) Modulo 2)*16)
1482 #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
1483 #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
1484 #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
1485 #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
1486 
1487 #define MSC_RT Fld (2, 0) /* ROM/static memory Type */
1488 #define MSC_NonBrst /* Non-Burst static memory */ \
1489  (0 << FShft (MSC_RT))
1490 #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
1491  (1 << FShft (MSC_RT))
1492 #define MSC_Brst4 /* Burst-of-4 static memory */ \
1493  (2 << FShft (MSC_RT))
1494 #define MSC_Brst8 /* Burst-of-8 static memory */ \
1495  (3 << FShft (MSC_RT))
1496 #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
1497 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1498 #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1499 #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1500  /* First access - 1(.5) [Tmem] */
1501 #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
1502  /* static memory) [3..65 Tcpu] */ \
1503  ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1504 #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
1505  ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1506 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1507  /* static memory) [2..64 Tcpu] */ \
1508  ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1509 #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
1510  ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1511 #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1512  /* Next access - 1 [Tmem] */
1513 #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
1514  /* static memory) [2..64 Tcpu] */ \
1515  ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1516 #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
1517  ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1518 #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
1519  /* static memory) [2..64 Tcpu] */ \
1520  ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1521 #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
1522  ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1523 #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
1524  /* time/2 [Tmem] */
1525 #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
1526  (((Tcpu)/4) << FShft (MSC_RRR))
1527 #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
1528  ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
1529 
1530 
1531 /*
1532  * Personal Computer Memory Card International Association (PCMCIA) control
1533  * register
1534  *
1535  * Register
1536  * MECR Memory system: Expansion memory bus (PCMCIA)
1537  * Configuration Register (read/write).
1538  *
1539  * Clocks
1540  * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1541  * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1542  * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
1543  */
1544 
1545  /* Memory system: */
1546 #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
1547 
1548 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
1549  Fld (15, (Nb)*16)
1550 #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
1551 #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
1552 
1553 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
1554 #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
1555  ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
1556 #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
1557  ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
1558 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
1559  /* [Tmem] */
1560 #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
1561  ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
1562 #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
1563  ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
1564 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
1565 #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
1566  ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
1567 #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
1568  ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
1569 
1570 /*
1571  * On SA1110 only
1572  */
1573 
1574 #define MDREFR __REG(0xA000001C)
1575 
1576 #define MDREFR_TRASR Fld (4, 0)
1577 #define MDREFR_DRI Fld (12, 4)
1578 #define MDREFR_E0PIN (1 << 16)
1579 #define MDREFR_K0RUN (1 << 17)
1580 #define MDREFR_K0DB2 (1 << 18)
1581 #define MDREFR_E1PIN (1 << 20)
1582 #define MDREFR_K1RUN (1 << 21)
1583 #define MDREFR_K1DB2 (1 << 22)
1584 #define MDREFR_K2RUN (1 << 25)
1585 #define MDREFR_K2DB2 (1 << 26)
1586 #define MDREFR_EAPD (1 << 28)
1587 #define MDREFR_KAPD (1 << 29)
1588 #define MDREFR_SLFRSH (1 << 31)
1589 
1590 
1591 /*
1592  * Direct Memory Access (DMA) control registers
1593  */
1594 #define DMA_SIZE (6 * 0x20)
1595 #define DMA_PHYS 0xb0000000
1596 
1597 
1598 /*
1599  * Liquid Crystal Display (LCD) control registers
1600  *
1601  * Registers
1602  * LCCR0 Liquid Crystal Display (LCD) Control Register 0
1603  * (read/write).
1604  * [Bits LDM, BAM, and ERM are only implemented in
1605  * versions 2.0 (rev. = 8) and higher of the StrongARM
1606  * SA-1100.]
1607  * LCSR Liquid Crystal Display (LCD) Status Register
1608  * (read/write).
1609  * [Bit LDD can be only read in versions 1.0 (rev. = 1)
1610  * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
1611  * read and written (cleared) in versions 2.0 (rev. = 8)
1612  * and higher.]
1613  * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
1614  * (DMA) Base Address Register channel 1 (read/write).
1615  * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
1616  * (DMA) Current Address Register channel 1 (read).
1617  * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
1618  * (DMA) Base Address Register channel 2 (read/write).
1619  * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
1620  * (DMA) Current Address Register channel 2 (read).
1621  * LCCR1 Liquid Crystal Display (LCD) Control Register 1
1622  * (read/write).
1623  * [The LCCR1 register can be only written in
1624  * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1625  * StrongARM SA-1100, it can be written and read in
1626  * versions 2.0 (rev. = 8) and higher.]
1627  * LCCR2 Liquid Crystal Display (LCD) Control Register 2
1628  * (read/write).
1629  * [The LCCR1 register can be only written in
1630  * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1631  * StrongARM SA-1100, it can be written and read in
1632  * versions 2.0 (rev. = 8) and higher.]
1633  * LCCR3 Liquid Crystal Display (LCD) Control Register 3
1634  * (read/write).
1635  * [The LCCR1 register can be only written in
1636  * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1637  * StrongARM SA-1100, it can be written and read in
1638  * versions 2.0 (rev. = 8) and higher. Bit PCP is only
1639  * implemented in versions 2.0 (rev. = 8) and higher of
1640  * the StrongARM SA-1100.]
1641  *
1642  * Clocks
1643  * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1644  * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1645  * fpix, Tpix Frequency, period of the pixel clock.
1646  * fln, Tln Frequency, period of the line clock.
1647  * fac, Tac Frequency, period of the AC bias clock.
1648  */
1649 
1650 #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
1651 #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
1652  /* [byte] */ \
1653  (16*LCD_PEntrySp)
1654 #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
1655  /* [byte] */ \
1656  (256*LCD_PEntrySp)
1657 #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
1658  /* dummy-Palette Space [byte] */ \
1659  (16*LCD_PEntrySp)
1660 
1661 #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
1662 #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
1663 #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
1664 #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
1665 #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
1666 #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
1667  (0 << FShft (LCD_PBS))
1668 #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
1669  (1 << FShft (LCD_PBS))
1670 #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
1671  (2 << FShft (LCD_PBS))
1672 
1673 #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
1674 #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
1675 #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
1676 #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
1677 #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
1678 #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
1679 #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
1680 #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
1681 #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
1682 #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
1683 #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
1684 #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
1685 #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
1686 #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
1687 #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
1688 #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
1689  /* (Alternative) */
1690 
1691 #define LCCR0_LEN 0x00000001 /* LCD ENable */
1692 #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
1693 #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
1694 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
1695 #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
1696  /* Select */
1697 #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
1698 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
1699 #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
1700  /* interrupt Mask (disable) */
1701 #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
1702  /* interrupt Mask (disable) */
1703 #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
1704  /* IUU, OOL, OUL, OOU, and OUU) */
1705  /* interrupt Mask (disable) */
1706 #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
1707 #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
1708 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
1709 #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
1710 #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
1711 #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
1712 #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
1713  /* display mode) */
1714 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1715  /* display */
1716 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
1717  /* display */
1718 #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
1719  /* [Tmem] */
1720 #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
1721  /* [0..510 Tcpu] */ \
1722  ((Tcpu)/2 << FShft (LCCR0_PDD))
1723 
1724 #define LCSR_LDD 0x00000001 /* LCD Disable Done */
1725 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
1726 #define LCSR_BER 0x00000004 /* Bus ERror */
1727 #define LCSR_ABC 0x00000008 /* AC Bias clock Count */
1728 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
1729  /* panel */
1730 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
1731  /* panel */
1732 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
1733  /* panel */
1734 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
1735  /* panel */
1736 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
1737  /* panel */
1738 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
1739  /* panel */
1740 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
1741  /* panel */
1742 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
1743  /* panel */
1744 
1745 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
1746 #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
1747  (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
1748 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
1749  /* pulse Width - 1 [Tpix] (L_LCLK) */
1750 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
1751  /* pulse Width [1..64 Tpix] */ \
1752  (((Tpix) - 1) << FShft (LCCR1_HSW))
1753 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1754  /* count - 1 [Tpix] */
1755 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1756  /* [1..256 Tpix] */ \
1757  (((Tpix) - 1) << FShft (LCCR1_ELW))
1758 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1759  /* Wait count - 1 [Tpix] */
1760 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1761  /* [1..256 Tpix] */ \
1762  (((Tpix) - 1) << FShft (LCCR1_BLW))
1763 
1764 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1765 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
1766  (((Line) - 1) << FShft (LCCR2_LPP))
1767 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
1768  /* Width - 1 [Tln] (L_FCLK) */
1769 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
1770  /* Width [1..64 Tln] */ \
1771  (((Tln) - 1) << FShft (LCCR2_VSW))
1772 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1773  /* count [Tln] */
1774 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1775  /* [0..255 Tln] */ \
1776  ((Tln) << FShft (LCCR2_EFW))
1777 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1778  /* Wait count [Tln] */
1779 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1780  /* [0..255 Tln] */ \
1781  ((Tln) << FShft (LCCR2_BFW))
1782 
1783 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
1784  /* [1..255] (L_PCLK) */
1785  /* fpix = fcpu/(2*(PCD + 2)) */
1786  /* Tpix = 2*(PCD + 2)*Tcpu */
1787 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
1788  (((Div) - 4)/2 << FShft (LCCR3_PCD))
1789  /* fpix = fcpu/(2*Floor (Div/2)) */
1790  /* Tpix = 2*Floor (Div/2)*Tcpu */
1791 #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
1792  (((Div) - 3)/2 << FShft (LCCR3_PCD))
1793  /* fpix = fcpu/(2*Ceil (Div/2)) */
1794  /* Tpix = 2*Ceil (Div/2)*Tcpu */
1795 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
1796  /* [Tln] (L_BIAS) */
1797 #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
1798  (((Div) - 2)/2 << FShft (LCCR3_ACB))
1799  /* fac = fln/(2*Floor (Div/2)) */
1800  /* Tac = 2*Floor (Div/2)*Tln */
1801 #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
1802  (((Div) - 1)/2 << FShft (LCCR3_ACB))
1803  /* fac = fln/(2*Ceil (Div/2)) */
1804  /* Tac = 2*Ceil (Div/2)*Tln */
1805 #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
1806  /* Interrupt */
1807 #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
1808  /* Off */ \
1809  (0 << FShft (LCCR3_API))
1810 #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
1811  /* [1..15] */ \
1812  ((Trans) << FShft (LCCR3_API))
1813 #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
1814  /* Polarity (L_FCLK) */
1815 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1816  /* active High */
1817 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
1818  /* active Low */
1819 #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
1820  /* pulse Polarity (L_LCLK) */
1821 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
1822  /* pulse active High */
1823 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
1824  /* pulse active Low */
1825 #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
1826 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1827 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
1828 #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
1829  /* active display mode) */
1830 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
1831 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
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