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ad9523.h
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1 /*
2  * AD9523 SPI Low Jitter Clock Generator
3  *
4  * Copyright 2012 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2.
7  */
8 
9 #ifndef IIO_FREQUENCY_AD9523_H_
10 #define IIO_FREQUENCY_AD9523_H_
11 
12 enum outp_drv_mode {
13  TRISTATE,
14  LVPECL_8mA,
15  LVDS_4mA,
16  LVDS_7mA,
17  HSTL0_16mA,
18  HSTL1_8mA,
19  CMOS_CONF1,
20  CMOS_CONF2,
21  CMOS_CONF3,
22  CMOS_CONF4,
23  CMOS_CONF5,
24  CMOS_CONF6,
25  CMOS_CONF7,
26  CMOS_CONF8,
27  CMOS_CONF9
28 };
29 
30 enum ref_sel_mode {
31  NONEREVERTIVE_STAY_ON_REFB,
32  REVERT_TO_REFA,
33  SELECT_REFA,
34  SELECT_REFB,
35  EXT_REF_SEL
36 };
37 
54 struct ad9523_channel_spec {
55  unsigned channel_num;
56  bool divider_output_invert_en;
57  bool sync_ignore_en;
58  bool low_power_mode_en;
59  /* CH0..CH3 VCXO, CH4..CH9 VCO2 */
60  bool use_alt_clock_src;
61  bool output_dis;
62  enum outp_drv_mode driver_mode;
63  unsigned char divider_phase;
64  unsigned short channel_divider;
65  char extended_name[16];
66 };
67 
68 enum pll1_rzero_resistor {
69  RZERO_883_OHM,
70  RZERO_677_OHM,
71  RZERO_341_OHM,
72  RZERO_135_OHM,
73  RZERO_10_OHM,
74  RZERO_USE_EXT_RES = 8,
75 };
76 
77 enum rpole2_resistor {
78  RPOLE2_900_OHM,
79  RPOLE2_450_OHM,
80  RPOLE2_300_OHM,
81  RPOLE2_225_OHM,
82 };
83 
84 enum rzero_resistor {
85  RZERO_3250_OHM,
86  RZERO_2750_OHM,
87  RZERO_2250_OHM,
88  RZERO_2100_OHM,
89  RZERO_3000_OHM,
90  RZERO_2500_OHM,
91  RZERO_2000_OHM,
92  RZERO_1850_OHM,
93 };
94 
95 enum cpole1_capacitor {
96  CPOLE1_0_PF,
97  CPOLE1_8_PF,
98  CPOLE1_16_PF,
99  CPOLE1_24_PF,
100  _CPOLE1_24_PF, /* place holder */
101  CPOLE1_32_PF,
102  CPOLE1_40_PF,
103  CPOLE1_48_PF,
104 };
105 
143 struct ad9523_platform_data {
144  unsigned long vcxo_freq;
145 
146  /* Differential/ Single-Ended Input Configuration */
147  bool refa_diff_rcv_en;
148  bool refb_diff_rcv_en;
149  bool zd_in_diff_en;
150  bool osc_in_diff_en;
151 
152  /*
153  * Valid if differential input disabled
154  * if false defaults to pos input
155  */
156  bool refa_cmos_neg_inp_en;
157  bool refb_cmos_neg_inp_en;
158  bool zd_in_cmos_neg_inp_en;
159  bool osc_in_cmos_neg_inp_en;
160 
161  /* PLL1 Setting */
162  unsigned short refa_r_div;
163  unsigned short refb_r_div;
164  unsigned short pll1_feedback_div;
165  unsigned short pll1_charge_pump_current_nA;
166  bool zero_delay_mode_internal_en;
167  bool osc_in_feedback_en;
168  enum pll1_rzero_resistor pll1_loop_filter_rzero;
169 
170  /* Reference */
171  enum ref_sel_mode ref_mode;
172 
173  /* PLL2 Setting */
174  unsigned int pll2_charge_pump_current_nA;
175  unsigned char pll2_ndiv_a_cnt;
176  unsigned char pll2_ndiv_b_cnt;
177  bool pll2_freq_doubler_en;
178  unsigned char pll2_r2_div;
179  unsigned char pll2_vco_diff_m1; /* 3..5 */
180  unsigned char pll2_vco_diff_m2; /* 3..5 */
181 
182  /* Loop Filter PLL2 */
183  enum rpole2_resistor rpole2;
184  enum rzero_resistor rzero;
185  enum cpole1_capacitor cpole1;
186  bool rzero_bypass_en;
187 
188  /* Output Channel Configuration */
189  int num_channels;
190  struct ad9523_channel_spec *channels;
191 
192  char name[SPI_NAME_SIZE];
193 };
194 
195 #endif /* IIO_FREQUENCY_AD9523_H_ */
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