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aic94xx_reg_def.h
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1 /*
2  * Aic94xx SAS/SATA driver hardware registers definitions.
3  *
4  * Copyright (C) 2004 Adaptec, Inc. All rights reserved.
5  * Copyright (C) 2004 David Chaw <[email protected]>
6  * Copyright (C) 2005 Luben Tuikov <[email protected]>
7  *
8  * Luben Tuikov: Some register value updates to make it work with the window
9  * agnostic register r/w functions. Some register corrections, sizes,
10  * etc.
11  *
12  * This file is licensed under GPLv2.
13  *
14  * This file is part of the aic94xx driver.
15  *
16  * The aic94xx driver is free software; you can redistribute it and/or
17  * modify it under the terms of the GNU General Public License as
18  * published by the Free Software Foundation; version 2 of the
19  * License.
20  *
21  * The aic94xx driver is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24  * General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with the aic94xx driver; if not, write to the Free Software
28  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29  *
30  * $Id: //depot/aic94xx/aic94xx_reg_def.h#27 $
31  *
32  */
33 
34 #ifndef _ADP94XX_REG_DEF_H_
35 #define _ADP94XX_REG_DEF_H_
36 
37 /*
38  * Common definitions.
39  */
40 #define CSEQ_MODE_PAGE_SIZE 0x200 /* CSEQ mode page size */
41 #define LmSEQ_MODE_PAGE_SIZE 0x200 /* LmSEQ mode page size */
42 #define LmSEQ_HOST_REG_SIZE 0x4000 /* LmSEQ Host Register size */
43 
44 /********************* COM_SAS registers definition *************************/
45 
46 /* The base is REG_BASE_ADDR, defined in aic94xx_reg.h.
47  */
48 
49 /*
50  * CHIM Registers, Address Range : (0x00-0xFF)
51  */
52 #define COMBIST (REG_BASE_ADDR + 0x00)
53 
54 /* bits 31:24 */
55 #define L7BLKRST 0x80000000
56 #define L6BLKRST 0x40000000
57 #define L5BLKRST 0x20000000
58 #define L4BLKRST 0x10000000
59 #define L3BLKRST 0x08000000
60 #define L2BLKRST 0x04000000
61 #define L1BLKRST 0x02000000
62 #define L0BLKRST 0x01000000
63 #define LmBLKRST 0xFF000000
64 #define LmBLKRST_COMBIST(phyid) (1 << (24 + phyid))
65 
66 #define OCMBLKRST 0x00400000
67 #define CTXMEMBLKRST 0x00200000
68 #define CSEQBLKRST 0x00100000
69 #define EXSIBLKRST 0x00040000
70 #define DPIBLKRST 0x00020000
71 #define DFIFBLKRST 0x00010000
72 #define HARDRST 0x00000200
73 #define COMBLKRST 0x00000100
74 #define FRCDFPERR 0x00000080
75 #define FRCCIOPERR 0x00000020
76 #define FRCBISTERR 0x00000010
77 #define COMBISTEN 0x00000004
78 #define COMBISTDONE 0x00000002 /* ro */
79 #define COMBISTFAIL 0x00000001 /* ro */
80 
81 #define COMSTAT (REG_BASE_ADDR + 0x04)
82 
83 #define REQMBXREAD 0x00000040
84 #define RSPMBXAVAIL 0x00000020
85 #define CSBUFPERR 0x00000008
86 #define OVLYERR 0x00000004
87 #define CSERR 0x00000002
88 #define OVLYDMADONE 0x00000001
89 
90 #define COMSTAT_MASK (REQMBXREAD | RSPMBXAVAIL | \
91  CSBUFPERR | OVLYERR | CSERR |\
92  OVLYDMADONE)
93 
94 #define COMSTATEN (REG_BASE_ADDR + 0x08)
95 
96 #define EN_REQMBXREAD 0x00000040
97 #define EN_RSPMBXAVAIL 0x00000020
98 #define EN_CSBUFPERR 0x00000008
99 #define EN_OVLYERR 0x00000004
100 #define EN_CSERR 0x00000002
101 #define EN_OVLYDONE 0x00000001
102 
103 #define SCBPRO (REG_BASE_ADDR + 0x0C)
104 
105 #define SCBCONS_MASK 0xFFFF0000
106 #define SCBPRO_MASK 0x0000FFFF
107 
108 #define CHIMREQMBX (REG_BASE_ADDR + 0x10)
109 
110 #define CHIMRSPMBX (REG_BASE_ADDR + 0x14)
111 
112 #define CHIMINT (REG_BASE_ADDR + 0x18)
113 
114 #define EXT_INT0 0x00000800
115 #define EXT_INT1 0x00000400
116 #define PORRSTDET 0x00000200
117 #define HARDRSTDET 0x00000100
118 #define DLAVAILQ 0x00000080 /* ro */
119 #define HOSTERR 0x00000040
120 #define INITERR 0x00000020
121 #define DEVINT 0x00000010
122 #define COMINT 0x00000008
123 #define DEVTIMER2 0x00000004
124 #define DEVTIMER1 0x00000002
125 #define DLAVAIL 0x00000001
126 
127 #define CHIMINT_MASK (HOSTERR | INITERR | DEVINT | COMINT |\
128  DEVTIMER2 | DEVTIMER1 | DLAVAIL)
129 
130 #define DEVEXCEPT_MASK (HOSTERR | INITERR | DEVINT | COMINT)
131 
132 #define CHIMINTEN (REG_BASE_ADDR + 0x1C)
133 
134 #define RST_EN_EXT_INT1 0x01000000
135 #define RST_EN_EXT_INT0 0x00800000
136 #define RST_EN_HOSTERR 0x00400000
137 #define RST_EN_INITERR 0x00200000
138 #define RST_EN_DEVINT 0x00100000
139 #define RST_EN_COMINT 0x00080000
140 #define RST_EN_DEVTIMER2 0x00040000
141 #define RST_EN_DEVTIMER1 0x00020000
142 #define RST_EN_DLAVAIL 0x00010000
143 #define SET_EN_EXT_INT1 0x00000100
144 #define SET_EN_EXT_INT0 0x00000080
145 #define SET_EN_HOSTERR 0x00000040
146 #define SET_EN_INITERR 0x00000020
147 #define SET_EN_DEVINT 0x00000010
148 #define SET_EN_COMINT 0x00000008
149 #define SET_EN_DEVTIMER2 0x00000004
150 #define SET_EN_DEVTIMER1 0x00000002
151 #define SET_EN_DLAVAIL 0x00000001
152 
153 #define RST_CHIMINTEN (RST_EN_HOSTERR | RST_EN_INITERR | \
154  RST_EN_DEVINT | RST_EN_COMINT | \
155  RST_EN_DEVTIMER2 | RST_EN_DEVTIMER1 |\
156  RST_EN_DLAVAIL)
157 
158 #define SET_CHIMINTEN (SET_EN_HOSTERR | SET_EN_INITERR |\
159  SET_EN_DEVINT | SET_EN_COMINT |\
160  SET_EN_DLAVAIL)
161 
162 #define OVLYDMACTL (REG_BASE_ADDR + 0x20)
163 
164 #define OVLYADR_MASK 0x07FF0000
165 #define OVLYLSEQ_MASK 0x0000FF00
166 #define OVLYCSEQ 0x00000080
167 #define OVLYHALTERR 0x00000040
168 #define PIOCMODE 0x00000020
169 #define RESETOVLYDMA 0x00000008 /* wo */
170 #define STARTOVLYDMA 0x00000004
171 #define STOPOVLYDMA 0x00000002 /* wo */
172 #define OVLYDMAACT 0x00000001 /* ro */
173 
174 #define OVLYDMACNT (REG_BASE_ADDR + 0x24)
175 
176 #define OVLYDOMAIN1 0x20000000 /* ro */
177 #define OVLYDOMAIN0 0x10000000
178 #define OVLYBUFADR_MASK 0x007F0000
179 #define OVLYDMACNT_MASK 0x00003FFF
180 
181 #define OVLYDMAADR (REG_BASE_ADDR + 0x28)
182 
183 #define DMAERR (REG_BASE_ADDR + 0x30)
184 
185 #define OVLYERRSTAT_MASK 0x0000FF00 /* ro */
186 #define CSERRSTAT_MASK 0x000000FF /* ro */
187 
188 #define SPIODATA (REG_BASE_ADDR + 0x34)
189 
190 /* 0x38 - 0x3C are reserved */
191 
192 #define T1CNTRLR (REG_BASE_ADDR + 0x40)
193 
194 #define T1DONE 0x00010000 /* ro */
195 #define TIMER64 0x00000400
196 #define T1ENABLE 0x00000200
197 #define T1RELOAD 0x00000100
198 #define T1PRESCALER_MASK 0x00000003
199 
200 #define T1CMPR (REG_BASE_ADDR + 0x44)
201 
202 #define T1CNTR (REG_BASE_ADDR + 0x48)
203 
204 #define T2CNTRLR (REG_BASE_ADDR + 0x4C)
205 
206 #define T2DONE 0x00010000 /* ro */
207 #define T2ENABLE 0x00000200
208 #define T2RELOAD 0x00000100
209 #define T2PRESCALER_MASK 0x00000003
210 
211 #define T2CMPR (REG_BASE_ADDR + 0x50)
212 
213 #define T2CNTR (REG_BASE_ADDR + 0x54)
214 
215 /* 0x58h - 0xFCh are reserved */
216 
217 /*
218  * DCH_SAS Registers, Address Range : (0x800-0xFFF)
219  */
220 #define CMDCTXBASE (REG_BASE_ADDR + 0x800)
221 
222 #define DEVCTXBASE (REG_BASE_ADDR + 0x808)
223 
224 #define CTXDOMAIN (REG_BASE_ADDR + 0x810)
225 
226 #define DEVCTXDOMAIN1 0x00000008 /* ro */
227 #define DEVCTXDOMAIN0 0x00000004
228 #define CMDCTXDOMAIN1 0x00000002 /* ro */
229 #define CMDCTXDOMAIN0 0x00000001
230 
231 #define DCHCTL (REG_BASE_ADDR + 0x814)
232 
233 #define OCMBISTREPAIR 0x00080000
234 #define OCMBISTEN 0x00040000
235 #define OCMBISTDN 0x00020000 /* ro */
236 #define OCMBISTFAIL 0x00010000 /* ro */
237 #define DDBBISTEN 0x00004000
238 #define DDBBISTDN 0x00002000 /* ro */
239 #define DDBBISTFAIL 0x00001000 /* ro */
240 #define SCBBISTEN 0x00000400
241 #define SCBBISTDN 0x00000200 /* ro */
242 #define SCBBISTFAIL 0x00000100 /* ro */
243 
244 #define MEMSEL_MASK 0x000000E0
245 #define MEMSEL_CCM_LSEQ 0x00000000
246 #define MEMSEL_CCM_IOP 0x00000020
247 #define MEMSEL_CCM_SASCTL 0x00000040
248 #define MEMSEL_DCM_LSEQ 0x00000060
249 #define MEMSEL_DCM_IOP 0x00000080
250 #define MEMSEL_OCM 0x000000A0
251 
252 #define FRCERR 0x00000010
253 #define AUTORLS 0x00000001
254 
255 #define DCHREVISION (REG_BASE_ADDR + 0x818)
256 
257 #define DCHREVISION_MASK 0x000000FF
258 
259 #define DCHSTATUS (REG_BASE_ADDR + 0x81C)
260 
261 #define EN_CFIFTOERR 0x00020000
262 #define CFIFTOERR 0x00000200
263 #define CSEQINT 0x00000100 /* ro */
264 #define LSEQ7INT 0x00000080 /* ro */
265 #define LSEQ6INT 0x00000040 /* ro */
266 #define LSEQ5INT 0x00000020 /* ro */
267 #define LSEQ4INT 0x00000010 /* ro */
268 #define LSEQ3INT 0x00000008 /* ro */
269 #define LSEQ2INT 0x00000004 /* ro */
270 #define LSEQ1INT 0x00000002 /* ro */
271 #define LSEQ0INT 0x00000001 /* ro */
272 
273 #define LSEQINT_MASK (LSEQ7INT | LSEQ6INT | LSEQ5INT |\
274  LSEQ4INT | LSEQ3INT | LSEQ2INT |\
275  LSEQ1INT | LSEQ0INT)
276 
277 #define DCHDFIFDEBUG (REG_BASE_ADDR + 0x820)
278 #define ENFAIRMST 0x00FF0000
279 #define DISWRMST9 0x00000200
280 #define DISWRMST8 0x00000100
281 #define DISRDMST 0x000000FF
282 
283 #define ATOMICSTATCTL (REG_BASE_ADDR + 0x824)
284 /* 8 bit wide */
285 #define AUTOINC 0x80
286 #define ATOMICERR 0x04
287 #define ATOMICWIN 0x02
288 #define ATOMICDONE 0x01
289 
290 
291 #define ALTCIOADR (REG_BASE_ADDR + 0x828)
292 /* 16 bit; bits 8:0 define CIO addr space of CSEQ */
293 
294 #define ASCBPTR (REG_BASE_ADDR + 0x82C)
295 /* 16 bit wide */
296 
297 #define ADDBPTR (REG_BASE_ADDR + 0x82E)
298 /* 16 bit wide */
299 
300 #define ANEWDATA (REG_BASE_ADDR + 0x830)
301 /* 16 bit */
302 
303 #define AOLDDATA (REG_BASE_ADDR + 0x834)
304 /* 16 bit */
305 
306 #define CTXACCESS (REG_BASE_ADDR + 0x838)
307 /* 32 bit */
308 
309 /* 0x83Ch - 0xFFCh are reserved */
310 
311 /*
312  * ARP2 External Processor Registers, Address Range : (0x00-0x1F)
313  */
314 #define ARP2CTL 0x00
315 
316 #define FRCSCRPERR 0x00040000
317 #define FRCARP2PERR 0x00020000
318 #define FRCARP2ILLOPC 0x00010000
319 #define ENWAITTO 0x00008000
320 #define PERRORDIS 0x00004000
321 #define FAILDIS 0x00002000
322 #define CIOPERRDIS 0x00001000
323 #define BREAKEN3 0x00000800
324 #define BREAKEN2 0x00000400
325 #define BREAKEN1 0x00000200
326 #define BREAKEN0 0x00000100
327 #define EPAUSE 0x00000008
328 #define PAUSED 0x00000004 /* ro */
329 #define STEP 0x00000002
330 #define ARP2RESET 0x00000001 /* wo */
331 
332 #define ARP2INT 0x04
333 
334 #define HALTCODE_MASK 0x00FF0000 /* ro */
335 #define ARP2WAITTO 0x00000100
336 #define ARP2HALTC 0x00000080
337 #define ARP2ILLOPC 0x00000040
338 #define ARP2PERR 0x00000020
339 #define ARP2CIOPERR 0x00000010
340 #define ARP2BREAK3 0x00000008
341 #define ARP2BREAK2 0x00000004
342 #define ARP2BREAK1 0x00000002
343 #define ARP2BREAK0 0x00000001
344 
345 #define ARP2INTEN 0x08
346 
347 #define EN_ARP2WAITTO 0x00000100
348 #define EN_ARP2HALTC 0x00000080
349 #define EN_ARP2ILLOPC 0x00000040
350 #define EN_ARP2PERR 0x00000020
351 #define EN_ARP2CIOPERR 0x00000010
352 #define EN_ARP2BREAK3 0x00000008
353 #define EN_ARP2BREAK2 0x00000004
354 #define EN_ARP2BREAK1 0x00000002
355 #define EN_ARP2BREAK0 0x00000001
356 
357 #define ARP2BREAKADR01 0x0C
358 
359 #define BREAKADR1_MASK 0x0FFF0000
360 #define BREAKADR0_MASK 0x00000FFF
361 
362 #define ARP2BREAKADR23 0x10
363 
364 #define BREAKADR3_MASK 0x0FFF0000
365 #define BREAKADR2_MASK 0x00000FFF
366 
367 /* 0x14h - 0x1Ch are reserved */
368 
369 /*
370  * ARP2 Registers, Address Range : (0x00-0x1F)
371  * The definitions have the same address offset for CSEQ and LmSEQ
372  * CIO Bus Registers.
373  */
374 #define MODEPTR 0x00
375 
376 #define DSTMODE 0xF0
377 #define SRCMODE 0x0F
378 
379 #define ALTMODE 0x01
380 
381 #define ALTDMODE 0xF0
382 #define ALTSMODE 0x0F
383 
384 #define ATOMICXCHG 0x02
385 
386 #define FLAG 0x04
387 
388 #define INTCODE_MASK 0xF0
389 #define ALTMODEV2 0x04
390 #define CARRY_INT 0x02
391 #define CARRY 0x01
392 
393 #define ARP2INTCTL 0x05
394 
395 #define PAUSEDIS 0x80
396 #define RSTINTCTL 0x40
397 #define POPALTMODE 0x08
398 #define ALTMODEV 0x04
399 #define INTMASK 0x02
400 #define IRET 0x01
401 
402 #define STACK 0x06
403 
404 #define FUNCTION1 0x07
405 
406 #define PRGMCNT 0x08
407 
408 #define ACCUM 0x0A
409 
410 #define SINDEX 0x0C
411 
412 #define DINDEX 0x0E
413 
414 #define ALLONES 0x10
415 
416 #define ALLZEROS 0x11
417 
418 #define SINDIR 0x12
419 
420 #define DINDIR 0x13
421 
422 #define JUMLDIR 0x14
423 
424 #define ARP2HALTCODE 0x15
425 
426 #define CURRADDR 0x16
427 
428 #define LASTADDR 0x18
429 
430 #define NXTLADDR 0x1A
431 
432 #define DBGPORTPTR 0x1C
433 
434 #define DBGPORT 0x1D
435 
436 /*
437  * CIO Registers.
438  * The definitions have the same address offset for CSEQ and LmSEQ
439  * CIO Bus Registers.
440  */
441 #define MnSCBPTR 0x20
442 
443 #define MnDDBPTR 0x22
444 
445 #define SCRATCHPAGE 0x24
446 
447 #define MnSCRATCHPAGE 0x25
448 
449 #define SCRATCHPAGESV 0x26
450 
451 #define MnSCRATCHPAGESV 0x27
452 
453 #define MnDMAERRS 0x46
454 
455 #define MnSGDMAERRS 0x47
456 
457 #define MnSGBUF 0x53
458 
459 #define MnSGDMASTAT 0x5b
460 
461 #define MnDDMACTL 0x5c /* RAZOR.rspec.fm rev 1.5 is wrong */
462 
463 #define MnDDMASTAT 0x5d /* RAZOR.rspec.fm rev 1.5 is wrong */
464 
465 #define MnDDMAMODE 0x5e /* RAZOR.rspec.fm rev 1.5 is wrong */
466 
467 #define MnDMAENG 0x60
468 
469 #define MnPIPECTL 0x61
470 
471 #define MnSGBADR 0x65
472 
473 #define MnSCB_SITE 0x100
474 
475 #define MnDDB_SITE 0x180
476 
477 /*
478  * The common definitions below have the same address offset for both
479  * CSEQ and LmSEQ.
480  */
481 #define BISTCTL0 0x4C
482 
483 #define BISTCTL1 0x50
484 
485 #define MAPPEDSCR 0x800
486 
487 /*
488  * CSEQ Host Register, Address Range : (0x000-0xFFC)
489  */
490 #define CSEQ_HOST_REG_BASE_ADR 0xB8001000
491 
492 #define CARP2CTL (CSEQ_HOST_REG_BASE_ADR + ARP2CTL)
493 
494 #define CARP2INT (CSEQ_HOST_REG_BASE_ADR + ARP2INT)
495 
496 #define CARP2INTEN (CSEQ_HOST_REG_BASE_ADR + ARP2INTEN)
497 
498 #define CARP2BREAKADR01 (CSEQ_HOST_REG_BASE_ADR+ARP2BREAKADR01)
499 
500 #define CARP2BREAKADR23 (CSEQ_HOST_REG_BASE_ADR+ARP2BREAKADR23)
501 
502 #define CBISTCTL (CSEQ_HOST_REG_BASE_ADR + BISTCTL1)
503 
504 #define CSEQRAMBISTEN 0x00000040
505 #define CSEQRAMBISTDN 0x00000020 /* ro */
506 #define CSEQRAMBISTFAIL 0x00000010 /* ro */
507 #define CSEQSCRBISTEN 0x00000004
508 #define CSEQSCRBISTDN 0x00000002 /* ro */
509 #define CSEQSCRBISTFAIL 0x00000001 /* ro */
510 
511 #define CMAPPEDSCR (CSEQ_HOST_REG_BASE_ADR + MAPPEDSCR)
512 
513 /*
514  * CSEQ CIO Bus Registers, Address Range : (0x0000-0x1FFC)
515  * 16 modes, each mode is 512 bytes.
516  * Unless specified, the register should valid for all modes.
517  */
518 #define CSEQ_CIO_REG_BASE_ADR REG_BASE_ADDR_CSEQCIO
519 
520 #define CSEQm_CIO_REG(Mode, Reg) \
521  (CSEQ_CIO_REG_BASE_ADR + \
522  ((u32) (Mode) * CSEQ_MODE_PAGE_SIZE) + (u32) (Reg))
523 
524 #define CMODEPTR (CSEQ_CIO_REG_BASE_ADR + MODEPTR)
525 
526 #define CALTMODE (CSEQ_CIO_REG_BASE_ADR + ALTMODE)
527 
528 #define CATOMICXCHG (CSEQ_CIO_REG_BASE_ADR + ATOMICXCHG)
529 
530 #define CFLAG (CSEQ_CIO_REG_BASE_ADR + FLAG)
531 
532 #define CARP2INTCTL (CSEQ_CIO_REG_BASE_ADR + ARP2INTCTL)
533 
534 #define CSTACK (CSEQ_CIO_REG_BASE_ADR + STACK)
535 
536 #define CFUNCTION1 (CSEQ_CIO_REG_BASE_ADR + FUNCTION1)
537 
538 #define CPRGMCNT (CSEQ_CIO_REG_BASE_ADR + PRGMCNT)
539 
540 #define CACCUM (CSEQ_CIO_REG_BASE_ADR + ACCUM)
541 
542 #define CSINDEX (CSEQ_CIO_REG_BASE_ADR + SINDEX)
543 
544 #define CDINDEX (CSEQ_CIO_REG_BASE_ADR + DINDEX)
545 
546 #define CALLONES (CSEQ_CIO_REG_BASE_ADR + ALLONES)
547 
548 #define CALLZEROS (CSEQ_CIO_REG_BASE_ADR + ALLZEROS)
549 
550 #define CSINDIR (CSEQ_CIO_REG_BASE_ADR + SINDIR)
551 
552 #define CDINDIR (CSEQ_CIO_REG_BASE_ADR + DINDIR)
553 
554 #define CJUMLDIR (CSEQ_CIO_REG_BASE_ADR + JUMLDIR)
555 
556 #define CARP2HALTCODE (CSEQ_CIO_REG_BASE_ADR + ARP2HALTCODE)
557 
558 #define CCURRADDR (CSEQ_CIO_REG_BASE_ADR + CURRADDR)
559 
560 #define CLASTADDR (CSEQ_CIO_REG_BASE_ADR + LASTADDR)
561 
562 #define CNXTLADDR (CSEQ_CIO_REG_BASE_ADR + NXTLADDR)
563 
564 #define CDBGPORTPTR (CSEQ_CIO_REG_BASE_ADR + DBGPORTPTR)
565 
566 #define CDBGPORT (CSEQ_CIO_REG_BASE_ADR + DBGPORT)
567 
568 #define CSCRATCHPAGE (CSEQ_CIO_REG_BASE_ADR + SCRATCHPAGE)
569 
570 #define CMnSCBPTR(Mode) CSEQm_CIO_REG(Mode, MnSCBPTR)
571 
572 #define CMnDDBPTR(Mode) CSEQm_CIO_REG(Mode, MnDDBPTR)
573 
574 #define CMnSCRATCHPAGE(Mode) CSEQm_CIO_REG(Mode, MnSCRATCHPAGE)
575 
576 #define CLINKCON (CSEQ_CIO_REG_BASE_ADR + 0x28)
577 
578 #define CCIOAACESS (CSEQ_CIO_REG_BASE_ADR + 0x2C)
579 
580 /* mode 0-7 */
581 #define MnREQMBX 0x30
582 #define CMnREQMBX(Mode) CSEQm_CIO_REG(Mode, 0x30)
583 
584 /* mode 8 */
585 #define CSEQCON CSEQm_CIO_REG(8, 0x30)
586 
587 /* mode 0-7 */
588 #define MnRSPMBX 0x34
589 #define CMnRSPMBX(Mode) CSEQm_CIO_REG(Mode, 0x34)
590 
591 /* mode 8 */
592 #define CSEQCOMCTL CSEQm_CIO_REG(8, 0x34)
593 
594 /* mode 8 */
595 #define CSEQCOMSTAT CSEQm_CIO_REG(8, 0x35)
596 
597 /* mode 8 */
598 #define CSEQCOMINTEN CSEQm_CIO_REG(8, 0x36)
599 
600 /* mode 8 */
601 #define CSEQCOMDMACTL CSEQm_CIO_REG(8, 0x37)
602 
603 #define CSHALTERR 0x10
604 #define RESETCSDMA 0x08 /* wo */
605 #define STARTCSDMA 0x04
606 #define STOPCSDMA 0x02 /* wo */
607 #define CSDMAACT 0x01 /* ro */
608 
609 /* mode 0-7 */
610 #define MnINT 0x38
611 #define CMnINT(Mode) CSEQm_CIO_REG(Mode, 0x38)
612 
613 #define CMnREQMBXE 0x02
614 #define CMnRSPMBXF 0x01
615 #define CMnINT_MASK 0x00000003
616 
617 /* mode 8 */
618 #define CSEQREQMBX CSEQm_CIO_REG(8, 0x38)
619 
620 /* mode 0-7 */
621 #define MnINTEN 0x3C
622 #define CMnINTEN(Mode) CSEQm_CIO_REG(Mode, 0x3C)
623 
624 #define EN_CMnRSPMBXF 0x01
625 
626 /* mode 8 */
627 #define CSEQRSPMBX CSEQm_CIO_REG(8, 0x3C)
628 
629 /* mode 8 */
630 #define CSDMAADR CSEQm_CIO_REG(8, 0x40)
631 
632 /* mode 8 */
633 #define CSDMACNT CSEQm_CIO_REG(8, 0x48)
634 
635 /* mode 8 */
636 #define CSEQDLCTL CSEQm_CIO_REG(8, 0x4D)
637 
638 #define DONELISTEND 0x10
639 #define DONELISTSIZE_MASK 0x0F
640 #define DONELISTSIZE_8ELEM 0x01
641 #define DONELISTSIZE_16ELEM 0x02
642 #define DONELISTSIZE_32ELEM 0x03
643 #define DONELISTSIZE_64ELEM 0x04
644 #define DONELISTSIZE_128ELEM 0x05
645 #define DONELISTSIZE_256ELEM 0x06
646 #define DONELISTSIZE_512ELEM 0x07
647 #define DONELISTSIZE_1024ELEM 0x08
648 #define DONELISTSIZE_2048ELEM 0x09
649 #define DONELISTSIZE_4096ELEM 0x0A
650 #define DONELISTSIZE_8192ELEM 0x0B
651 #define DONELISTSIZE_16384ELEM 0x0C
652 
653 /* mode 8 */
654 #define CSEQDLOFFS CSEQm_CIO_REG(8, 0x4E)
655 
656 /* mode 11 */
657 #define CM11INTVEC0 CSEQm_CIO_REG(11, 0x50)
658 
659 /* mode 11 */
660 #define CM11INTVEC1 CSEQm_CIO_REG(11, 0x52)
661 
662 /* mode 11 */
663 #define CM11INTVEC2 CSEQm_CIO_REG(11, 0x54)
664 
665 #define CCONMSK (CSEQ_CIO_REG_BASE_ADR + 0x60)
666 
667 #define CCONEXIST (CSEQ_CIO_REG_BASE_ADR + 0x61)
668 
669 #define CCONMODE (CSEQ_CIO_REG_BASE_ADR + 0x62)
670 
671 #define CTIMERCALC (CSEQ_CIO_REG_BASE_ADR + 0x64)
672 
673 #define CINTDIS (CSEQ_CIO_REG_BASE_ADR + 0x68)
674 
675 /* mode 8, 32x32 bits, 128 bytes of mapped buffer */
676 #define CSBUFFER CSEQm_CIO_REG(8, 0x80)
677 
678 #define CSCRATCH (CSEQ_CIO_REG_BASE_ADR + 0x1C0)
679 
680 /* mode 0-8 */
681 #define CMnSCRATCH(Mode) CSEQm_CIO_REG(Mode, 0x1E0)
682 
683 /*
684  * CSEQ Mapped Instruction RAM Page, Address Range : (0x0000-0x1FFC)
685  */
686 #define CSEQ_RAM_REG_BASE_ADR 0xB8004000
687 
688 /*
689  * The common definitions below have the same address offset for all the Link
690  * sequencers.
691  */
692 #define MODECTL 0x40
693 
694 #define DBGMODE 0x44
695 
696 #define CONTROL 0x48
697 #define LEDTIMER 0x00010000
698 #define LEDTIMERS_10us 0x00000000
699 #define LEDTIMERS_1ms 0x00000800
700 #define LEDTIMERS_100ms 0x00001000
701 #define LEDMODE_TXRX 0x00000000
702 #define LEDMODE_CONNECTED 0x00000200
703 #define LEDPOL 0x00000100
704 
705 #define LSEQRAM 0x1000
706 
707 /*
708  * LmSEQ Host Registers, Address Range : (0x0000-0x3FFC)
709  */
710 #define LSEQ0_HOST_REG_BASE_ADR 0xB8020000
711 #define LSEQ1_HOST_REG_BASE_ADR 0xB8024000
712 #define LSEQ2_HOST_REG_BASE_ADR 0xB8028000
713 #define LSEQ3_HOST_REG_BASE_ADR 0xB802C000
714 #define LSEQ4_HOST_REG_BASE_ADR 0xB8030000
715 #define LSEQ5_HOST_REG_BASE_ADR 0xB8034000
716 #define LSEQ6_HOST_REG_BASE_ADR 0xB8038000
717 #define LSEQ7_HOST_REG_BASE_ADR 0xB803C000
718 
719 #define LmARP2CTL(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
720  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
721  ARP2CTL)
722 
723 #define LmARP2INT(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
724  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
725  ARP2INT)
726 
727 #define LmARP2INTEN(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
728  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
729  ARP2INTEN)
730 
731 #define LmDBGMODE(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
732  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
733  DBGMODE)
734 
735 #define LmCONTROL(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
736  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
737  CONTROL)
738 
739 #define LmARP2BREAKADR01(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
740  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
741  ARP2BREAKADR01)
742 
743 #define LmARP2BREAKADR23(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
744  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
745  ARP2BREAKADR23)
746 
747 #define LmMODECTL(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
748  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
749  MODECTL)
750 
751 #define LmAUTODISCI 0x08000000
752 #define LmDSBLBITLT 0x04000000
753 #define LmDSBLANTT 0x02000000
754 #define LmDSBLCRTT 0x01000000
755 #define LmDSBLCONT 0x00000100
756 #define LmPRIMODE 0x00000080
757 #define LmDSBLHOLD 0x00000040
758 #define LmDISACK 0x00000020
759 #define LmBLIND48 0x00000010
760 #define LmRCVMODE_MASK 0x0000000C
761 #define LmRCVMODE_PLD 0x00000000
762 #define LmRCVMODE_HPC 0x00000004
763 
764 #define LmDBGMODE(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
765  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
766  DBGMODE)
767 
768 #define LmFRCPERR 0x80000000
769 #define LmMEMSEL_MASK 0x30000000
770 #define LmFRCRBPERR 0x00000000
771 #define LmFRCTBPERR 0x10000000
772 #define LmFRCSGBPERR 0x20000000
773 #define LmFRCARBPERR 0x30000000
774 #define LmRCVIDW 0x00080000
775 #define LmINVDWERR 0x00040000
776 #define LmRCVDISP 0x00004000
777 #define LmDISPERR 0x00002000
778 #define LmDSBLDSCR 0x00000800
779 #define LmDSBLSCR 0x00000400
780 #define LmFRCNAK 0x00000200
781 #define LmFRCROFS 0x00000100
782 #define LmFRCCRC 0x00000080
783 #define LmFRMTYPE_MASK 0x00000070
784 #define LmSG_DATA 0x00000000
785 #define LmSG_COMMAND 0x00000010
786 #define LmSG_TASK 0x00000020
787 #define LmSG_TGTXFER 0x00000030
788 #define LmSG_RESPONSE 0x00000040
789 #define LmSG_IDENADDR 0x00000050
790 #define LmSG_OPENADDR 0x00000060
791 #define LmDISCRCGEN 0x00000008
792 #define LmDISCRCCHK 0x00000004
793 #define LmSSXMTFRM 0x00000002
794 #define LmSSRCVFRM 0x00000001
795 
796 #define LmCONTROL(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
797  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
798  CONTROL)
799 
800 #define LmSTEPXMTFRM 0x00000002
801 #define LmSTEPRCVFRM 0x00000001
802 
803 #define LmBISTCTL0(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
804  ((LinkNum)*LmSEQ_HOST_REG_SIZE) + \
805  BISTCTL0)
806 
807 #define ARBBISTEN 0x40000000
808 #define ARBBISTDN 0x20000000 /* ro */
809 #define ARBBISTFAIL 0x10000000 /* ro */
810 #define TBBISTEN 0x00000400
811 #define TBBISTDN 0x00000200 /* ro */
812 #define TBBISTFAIL 0x00000100 /* ro */
813 #define RBBISTEN 0x00000040
814 #define RBBISTDN 0x00000020 /* ro */
815 #define RBBISTFAIL 0x00000010 /* ro */
816 #define SGBISTEN 0x00000004
817 #define SGBISTDN 0x00000002 /* ro */
818 #define SGBISTFAIL 0x00000001 /* ro */
819 
820 #define LmBISTCTL1(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
821  ((LinkNum)*LmSEQ_HOST_REG_SIZE) +\
822  BISTCTL1)
823 
824 #define LmRAMPAGE1 0x00000200
825 #define LmRAMPAGE0 0x00000100
826 #define LmIMEMBISTEN 0x00000040
827 #define LmIMEMBISTDN 0x00000020 /* ro */
828 #define LmIMEMBISTFAIL 0x00000010 /* ro */
829 #define LmSCRBISTEN 0x00000004
830 #define LmSCRBISTDN 0x00000002 /* ro */
831 #define LmSCRBISTFAIL 0x00000001 /* ro */
832 #define LmRAMPAGE (LmRAMPAGE1 + LmRAMPAGE0)
833 #define LmRAMPAGE_LSHIFT 0x8
834 
835 #define LmSCRATCH(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
836  ((LinkNum) * LmSEQ_HOST_REG_SIZE) +\
837  MAPPEDSCR)
838 
839 #define LmSEQRAM(LinkNum) (LSEQ0_HOST_REG_BASE_ADR + \
840  ((LinkNum) * LmSEQ_HOST_REG_SIZE) +\
841  LSEQRAM)
842 
843 /*
844  * LmSEQ CIO Bus Register, Address Range : (0x0000-0xFFC)
845  * 8 modes, each mode is 512 bytes.
846  * Unless specified, the register should valid for all modes.
847  */
848 #define LmSEQ_CIOBUS_REG_BASE 0x2000
849 
850 #define LmSEQ_PHY_BASE(Mode, LinkNum) \
851  (LSEQ0_HOST_REG_BASE_ADR + \
852  (LmSEQ_HOST_REG_SIZE * (u32) (LinkNum)) + \
853  LmSEQ_CIOBUS_REG_BASE + \
854  ((u32) (Mode) * LmSEQ_MODE_PAGE_SIZE))
855 
856 #define LmSEQ_PHY_REG(Mode, LinkNum, Reg) \
857  (LmSEQ_PHY_BASE(Mode, LinkNum) + (u32) (Reg))
858 
859 #define LmMODEPTR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, MODEPTR)
860 
861 #define LmALTMODE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ALTMODE)
862 
863 #define LmATOMICXCHG(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ATOMICXCHG)
864 
865 #define LmFLAG(LinkNum) LmSEQ_PHY_REG(0, LinkNum, FLAG)
866 
867 #define LmARP2INTCTL(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ARP2INTCTL)
868 
869 #define LmSTACK(LinkNum) LmSEQ_PHY_REG(0, LinkNum, STACK)
870 
871 #define LmFUNCTION1(LinkNum) LmSEQ_PHY_REG(0, LinkNum, FUNCTION1)
872 
873 #define LmPRGMCNT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, PRGMCNT)
874 
875 #define LmACCUM(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ACCUM)
876 
877 #define LmSINDEX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, SINDEX)
878 
879 #define LmDINDEX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DINDEX)
880 
881 #define LmALLONES(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ALLONES)
882 
883 #define LmALLZEROS(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ALLZEROS)
884 
885 #define LmSINDIR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, SINDIR)
886 
887 #define LmDINDIR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DINDIR)
888 
889 #define LmJUMLDIR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, JUMLDIR)
890 
891 #define LmARP2HALTCODE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, ARP2HALTCODE)
892 
893 #define LmCURRADDR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, CURRADDR)
894 
895 #define LmLASTADDR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, LASTADDR)
896 
897 #define LmNXTLADDR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, NXTLADDR)
898 
899 #define LmDBGPORTPTR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DBGPORTPTR)
900 
901 #define LmDBGPORT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, DBGPORT)
902 
903 #define LmSCRATCHPAGE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, SCRATCHPAGE)
904 
905 #define LmMnSCRATCHPAGE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, \
906  MnSCRATCHPAGE)
907 
908 #define LmTIMERCALC(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x28)
909 
910 #define LmREQMBX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x30)
911 
912 #define LmRSPMBX(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x34)
913 
914 #define LmMnINT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x38)
915 
916 #define CTXMEMSIZE 0x80000000 /* ro */
917 #define LmACKREQ 0x08000000
918 #define LmNAKREQ 0x04000000
919 #define LmMnXMTERR 0x02000000
920 #define LmM5OOBSVC 0x01000000
921 #define LmHWTINT 0x00800000
922 #define LmMnCTXDONE 0x00100000
923 #define LmM2REQMBXF 0x00080000
924 #define LmM2RSPMBXE 0x00040000
925 #define LmMnDMAERR 0x00020000
926 #define LmRCVPRIM 0x00010000
927 #define LmRCVERR 0x00008000
928 #define LmADDRRCV 0x00004000
929 #define LmMnHDRMISS 0x00002000
930 #define LmMnWAITSCB 0x00001000
931 #define LmMnRLSSCB 0x00000800
932 #define LmMnSAVECTX 0x00000400
933 #define LmMnFETCHSG 0x00000200
934 #define LmMnLOADCTX 0x00000100
935 #define LmMnCFGICL 0x00000080
936 #define LmMnCFGSATA 0x00000040
937 #define LmMnCFGEXPSATA 0x00000020
938 #define LmMnCFGCMPLT 0x00000010
939 #define LmMnCFGRBUF 0x00000008
940 #define LmMnSAVETTR 0x00000004
941 #define LmMnCFGRDAT 0x00000002
942 #define LmMnCFGHDR 0x00000001
943 
944 #define LmMnINTEN(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x3C)
945 
946 #define EN_LmACKREQ 0x08000000
947 #define EN_LmNAKREQ 0x04000000
948 #define EN_LmMnXMTERR 0x02000000
949 #define EN_LmM5OOBSVC 0x01000000
950 #define EN_LmHWTINT 0x00800000
951 #define EN_LmMnCTXDONE 0x00100000
952 #define EN_LmM2REQMBXF 0x00080000
953 #define EN_LmM2RSPMBXE 0x00040000
954 #define EN_LmMnDMAERR 0x00020000
955 #define EN_LmRCVPRIM 0x00010000
956 #define EN_LmRCVERR 0x00008000
957 #define EN_LmADDRRCV 0x00004000
958 #define EN_LmMnHDRMISS 0x00002000
959 #define EN_LmMnWAITSCB 0x00001000
960 #define EN_LmMnRLSSCB 0x00000800
961 #define EN_LmMnSAVECTX 0x00000400
962 #define EN_LmMnFETCHSG 0x00000200
963 #define EN_LmMnLOADCTX 0x00000100
964 #define EN_LmMnCFGICL 0x00000080
965 #define EN_LmMnCFGSATA 0x00000040
966 #define EN_LmMnCFGEXPSATA 0x00000020
967 #define EN_LmMnCFGCMPLT 0x00000010
968 #define EN_LmMnCFGRBUF 0x00000008
969 #define EN_LmMnSAVETTR 0x00000004
970 #define EN_LmMnCFGRDAT 0x00000002
971 #define EN_LmMnCFGHDR 0x00000001
972 
973 #define LmM0INTEN_MASK (EN_LmMnCFGCMPLT | EN_LmMnCFGRBUF | \
974  EN_LmMnSAVETTR | EN_LmMnCFGRDAT | \
975  EN_LmMnCFGHDR | EN_LmRCVERR | \
976  EN_LmADDRRCV | EN_LmMnHDRMISS | \
977  EN_LmMnRLSSCB | EN_LmMnSAVECTX | \
978  EN_LmMnFETCHSG | EN_LmMnLOADCTX | \
979  EN_LmHWTINT | EN_LmMnCTXDONE | \
980  EN_LmRCVPRIM | EN_LmMnCFGSATA | \
981  EN_LmMnCFGEXPSATA | EN_LmMnDMAERR)
982 
983 #define LmM1INTEN_MASK (EN_LmMnCFGCMPLT | EN_LmADDRRCV | \
984  EN_LmMnRLSSCB | EN_LmMnSAVECTX | \
985  EN_LmMnFETCHSG | EN_LmMnLOADCTX | \
986  EN_LmMnXMTERR | EN_LmHWTINT | \
987  EN_LmMnCTXDONE | EN_LmRCVPRIM | \
988  EN_LmRCVERR | EN_LmMnDMAERR)
989 
990 #define LmM2INTEN_MASK (EN_LmADDRRCV | EN_LmHWTINT | \
991  EN_LmM2REQMBXF | EN_LmRCVPRIM | \
992  EN_LmRCVERR)
993 
994 #define LmM5INTEN_MASK (EN_LmADDRRCV | EN_LmM5OOBSVC | \
995  EN_LmHWTINT | EN_LmRCVPRIM | \
996  EN_LmRCVERR)
997 
998 #define LmXMTPRIMD(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x40)
999 
1000 #define LmXMTPRIMCS(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x44)
1001 
1002 #define LmCONSTAT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x45)
1003 
1004 #define LmMnDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x46)
1005 
1006 #define LmMnSGDMAERRS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x47)
1007 
1008 #define LmM0EXPHDRP(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x48)
1009 
1010 #define LmM1SASALIGN(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x48)
1011 #define SAS_ALIGN_DEFAULT 0xFF
1012 
1013 #define LmM0MSKHDRP(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x49)
1014 
1015 #define LmM1STPALIGN(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x49)
1016 #define STP_ALIGN_DEFAULT 0x1F
1017 
1018 #define LmM0RCVHDRP(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x4A)
1019 
1020 #define LmM1XMTHDRP(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x4A)
1021 
1022 #define LmM0ICLADR(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x4B)
1023 
1024 #define LmM1ALIGNMODE(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x4B)
1025 
1026 #define LmDISALIGN 0x20
1027 #define LmROTSTPALIGN 0x10
1028 #define LmSTPALIGN 0x08
1029 #define LmROTNOTIFY 0x04
1030 #define LmDUALALIGN 0x02
1031 #define LmROTALIGN 0x01
1032 
1033 #define LmM0EXPRCVNT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x4C)
1034 
1035 #define LmM1XMTCNT(LinkNum) LmSEQ_PHY_REG(1, LinkNum, 0x4C)
1036 
1037 #define LmMnBUFSTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x4E)
1038 
1039 #define LmMnBUFPERR 0x01
1040 
1041 /* mode 0-1 */
1042 #define LmMnXFRLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x59)
1043 
1044 #define LmMnXFRLVL_128 0x05
1045 #define LmMnXFRLVL_256 0x04
1046 #define LmMnXFRLVL_512 0x03
1047 #define LmMnXFRLVL_1024 0x02
1048 #define LmMnXFRLVL_1536 0x01
1049 #define LmMnXFRLVL_2048 0x00
1050 
1051  /* mode 0-1 */
1052 #define LmMnSGDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5A)
1053 
1054 #define LmMnRESETSG 0x04
1055 #define LmMnSTOPSG 0x02
1056 #define LmMnSTARTSG 0x01
1057 
1058 /* mode 0-1 */
1059 #define LmMnSGDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5B)
1060 
1061 /* mode 0-1 */
1062 #define LmMnDDMACTL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5C)
1063 
1064 #define LmMnFLUSH 0x40 /* wo */
1065 #define LmMnRLSRTRY 0x20 /* wo */
1066 #define LmMnDISCARD 0x10 /* wo */
1067 #define LmMnRESETDAT 0x08 /* wo */
1068 #define LmMnSUSDAT 0x04 /* wo */
1069 #define LmMnSTOPDAT 0x02 /* wo */
1070 #define LmMnSTARTDAT 0x01 /* wo */
1071 
1072 /* mode 0-1 */
1073 #define LmMnDDMASTAT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5D)
1074 
1075 #define LmMnDPEMPTY 0x80
1076 #define LmMnFLUSHING 0x40
1077 #define LmMnDDMAREQ 0x20
1078 #define LmMnHDMAREQ 0x10
1079 #define LmMnDATFREE 0x08
1080 #define LmMnDATSUS 0x04
1081 #define LmMnDATACT 0x02
1082 #define LmMnDATEN 0x01
1083 
1084 /* mode 0-1 */
1085 #define LmMnDDMAMODE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x5E)
1086 
1087 #define LmMnDMATYPE_NORMAL 0x0000
1088 #define LmMnDMATYPE_HOST_ONLY_TX 0x0001
1089 #define LmMnDMATYPE_DEVICE_ONLY_TX 0x0002
1090 #define LmMnDMATYPE_INVALID 0x0003
1091 #define LmMnDMATYPE_MASK 0x0003
1092 
1093 #define LmMnDMAWRAP 0x0004
1094 #define LmMnBITBUCKET 0x0008
1095 #define LmMnDISHDR 0x0010
1096 #define LmMnSTPCRC 0x0020
1097 #define LmXTEST 0x0040
1098 #define LmMnDISCRC 0x0080
1099 #define LmMnENINTLK 0x0100
1100 #define LmMnADDRFRM 0x0400
1101 #define LmMnENXMTCRC 0x0800
1102 
1103 /* mode 0-1 */
1104 #define LmMnXFRCNT(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x70)
1105 
1106 /* mode 0-1 */
1107 #define LmMnDPSEL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7B)
1108 #define LmMnDPSEL_MASK 0x07
1109 #define LmMnEOLPRE 0x40
1110 #define LmMnEOSPRE 0x80
1111 
1112 /* Registers used in conjunction with LmMnDPSEL and LmMnDPACC registers */
1113 /* Receive Mode n = 0 */
1114 #define LmMnHRADDR 0x00
1115 #define LmMnHBYTECNT 0x01
1116 #define LmMnHREWIND 0x02
1117 #define LmMnDWADDR 0x03
1118 #define LmMnDSPACECNT 0x04
1119 #define LmMnDFRMSIZE 0x05
1120 
1121 /* Registers used in conjunction with LmMnDPSEL and LmMnDPACC registers */
1122 /* Transmit Mode n = 1 */
1123 #define LmMnHWADDR 0x00
1124 #define LmMnHSPACECNT 0x01
1125 /* #define LmMnHREWIND 0x02 */
1126 #define LmMnDRADDR 0x03
1127 #define LmMnDBYTECNT 0x04
1128 /* #define LmMnDFRMSIZE 0x05 */
1129 
1130 /* mode 0-1 */
1131 #define LmMnDPACC(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x78)
1132 #define LmMnDPACC_MASK 0x00FFFFFF
1133 
1134 /* mode 0-1 */
1135 #define LmMnHOLDLVL(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7D)
1136 
1137 #define LmPRMSTAT0(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x80)
1138 #define LmPRMSTAT0BYTE0 0x80
1139 #define LmPRMSTAT0BYTE1 0x81
1140 #define LmPRMSTAT0BYTE2 0x82
1141 #define LmPRMSTAT0BYTE3 0x83
1142 
1143 #define LmFRAMERCVD 0x80000000
1144 #define LmXFRRDYRCVD 0x40000000
1145 #define LmUNKNOWNP 0x20000000
1146 #define LmBREAK 0x10000000
1147 #define LmDONE 0x08000000
1148 #define LmOPENACPT 0x04000000
1149 #define LmOPENRJCT 0x02000000
1150 #define LmOPENRTRY 0x01000000
1151 #define LmCLOSERV1 0x00800000
1152 #define LmCLOSERV0 0x00400000
1153 #define LmCLOSENORM 0x00200000
1154 #define LmCLOSECLAF 0x00100000
1155 #define LmNOTIFYRV2 0x00080000
1156 #define LmNOTIFYRV1 0x00040000
1157 #define LmNOTIFYRV0 0x00020000
1158 #define LmNOTIFYSPIN 0x00010000
1159 #define LmBROADRV4 0x00008000
1160 #define LmBROADRV3 0x00004000
1161 #define LmBROADRV2 0x00002000
1162 #define LmBROADRV1 0x00001000
1163 #define LmBROADSES 0x00000800
1164 #define LmBROADRVCH1 0x00000400
1165 #define LmBROADRVCH0 0x00000200
1166 #define LmBROADCH 0x00000100
1167 #define LmAIPRVWP 0x00000080
1168 #define LmAIPWP 0x00000040
1169 #define LmAIPWD 0x00000020
1170 #define LmAIPWC 0x00000010
1171 #define LmAIPRV2 0x00000008
1172 #define LmAIPRV1 0x00000004
1173 #define LmAIPRV0 0x00000002
1174 #define LmAIPNRML 0x00000001
1175 
1176 #define LmBROADCAST_MASK (LmBROADCH | LmBROADRVCH0 | \
1177  LmBROADRVCH1)
1178 
1179 #define LmPRMSTAT1(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0x84)
1180 #define LmPRMSTAT1BYTE0 0x84
1181 #define LmPRMSTAT1BYTE1 0x85
1182 #define LmPRMSTAT1BYTE2 0x86
1183 #define LmPRMSTAT1BYTE3 0x87
1184 
1185 #define LmFRMRCVDSTAT 0x80000000
1186 #define LmBREAK_DET 0x04000000
1187 #define LmCLOSE_DET 0x02000000
1188 #define LmDONE_DET 0x01000000
1189 #define LmXRDY 0x00040000
1190 #define LmSYNCSRST 0x00020000
1191 #define LmSYNC 0x00010000
1192 #define LmXHOLD 0x00008000
1193 #define LmRRDY 0x00004000
1194 #define LmHOLD 0x00002000
1195 #define LmROK 0x00001000
1196 #define LmRIP 0x00000800
1197 #define LmCRBLK 0x00000400
1198 #define LmACK 0x00000200
1199 #define LmNAK 0x00000100
1200 #define LmHARDRST 0x00000080
1201 #define LmERROR 0x00000040
1202 #define LmRERR 0x00000020
1203 #define LmPMREQP 0x00000010
1204 #define LmPMREQS 0x00000008
1205 #define LmPMACK 0x00000004
1206 #define LmPMNAK 0x00000002
1207 #define LmDMAT 0x00000001
1208 
1209 /* mode 1 */
1210 #define LmMnSATAFS(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x7E)
1211 #define LmMnXMTSIZE(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0x93)
1212 
1213 /* mode 0 */
1214 #define LmMnFRMERR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xB0)
1215 
1216 #define LmACRCERR 0x00000800
1217 #define LmPHYOVRN 0x00000400
1218 #define LmOBOVRN 0x00000200
1219 #define LmMnZERODATA 0x00000100
1220 #define LmSATAINTLK 0x00000080
1221 #define LmMnCRCERR 0x00000020
1222 #define LmRRDYOVRN 0x00000010
1223 #define LmMISSSOAF 0x00000008
1224 #define LmMISSSOF 0x00000004
1225 #define LmMISSEOAF 0x00000002
1226 #define LmMISSEOF 0x00000001
1227 
1228 #define LmFRMERREN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xB4)
1229 
1230 #define EN_LmACRCERR 0x00000800
1231 #define EN_LmPHYOVRN 0x00000400
1232 #define EN_LmOBOVRN 0x00000200
1233 #define EN_LmMnZERODATA 0x00000100
1234 #define EN_LmSATAINTLK 0x00000080
1235 #define EN_LmFRMBAD 0x00000040
1236 #define EN_LmMnCRCERR 0x00000020
1237 #define EN_LmRRDYOVRN 0x00000010
1238 #define EN_LmMISSSOAF 0x00000008
1239 #define EN_LmMISSSOF 0x00000004
1240 #define EN_LmMISSEOAF 0x00000002
1241 #define EN_LmMISSEOF 0x00000001
1242 
1243 #define LmFRMERREN_MASK (EN_LmSATAINTLK | EN_LmMnCRCERR | \
1244  EN_LmRRDYOVRN | EN_LmMISSSOF | \
1245  EN_LmMISSEOAF | EN_LmMISSEOF | \
1246  EN_LmACRCERR | LmPHYOVRN | \
1247  EN_LmOBOVRN | EN_LmMnZERODATA)
1248 
1249 #define LmHWTSTATEN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xC5)
1250 
1251 #define EN_LmDONETO 0x80
1252 #define EN_LmINVDISP 0x40
1253 #define EN_LmINVDW 0x20
1254 #define EN_LmDWSEVENT 0x08
1255 #define EN_LmCRTTTO 0x04
1256 #define EN_LmANTTTO 0x02
1257 #define EN_LmBITLTTO 0x01
1258 
1259 #define LmHWTSTATEN_MASK (EN_LmINVDISP | EN_LmINVDW | \
1260  EN_LmDWSEVENT | EN_LmCRTTTO | \
1261  EN_LmANTTTO | EN_LmDONETO | \
1262  EN_LmBITLTTO)
1263 
1264 #define LmHWTSTAT(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xC7)
1265 
1266 #define LmDONETO 0x80
1267 #define LmINVDISP 0x40
1268 #define LmINVDW 0x20
1269 #define LmDWSEVENT 0x08
1270 #define LmCRTTTO 0x04
1271 #define LmANTTTO 0x02
1272 #define LmBITLTTO 0x01
1273 
1274 #define LmMnDATABUFADR(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xC8)
1275 #define LmDATABUFADR_MASK 0x0FFF
1276 
1277 #define LmMnDATABUF(LinkNum, Mode) LmSEQ_PHY_REG(Mode, LinkNum, 0xCA)
1278 
1279 #define LmPRIMSTAT0EN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xE0)
1280 
1281 #define EN_LmUNKNOWNP 0x20000000
1282 #define EN_LmBREAK 0x10000000
1283 #define EN_LmDONE 0x08000000
1284 #define EN_LmOPENACPT 0x04000000
1285 #define EN_LmOPENRJCT 0x02000000
1286 #define EN_LmOPENRTRY 0x01000000
1287 #define EN_LmCLOSERV1 0x00800000
1288 #define EN_LmCLOSERV0 0x00400000
1289 #define EN_LmCLOSENORM 0x00200000
1290 #define EN_LmCLOSECLAF 0x00100000
1291 #define EN_LmNOTIFYRV2 0x00080000
1292 #define EN_LmNOTIFYRV1 0x00040000
1293 #define EN_LmNOTIFYRV0 0x00020000
1294 #define EN_LmNOTIFYSPIN 0x00010000
1295 #define EN_LmBROADRV4 0x00008000
1296 #define EN_LmBROADRV3 0x00004000
1297 #define EN_LmBROADRV2 0x00002000
1298 #define EN_LmBROADRV1 0x00001000
1299 #define EN_LmBROADRV0 0x00000800
1300 #define EN_LmBROADRVCH1 0x00000400
1301 #define EN_LmBROADRVCH0 0x00000200
1302 #define EN_LmBROADCH 0x00000100
1303 #define EN_LmAIPRVWP 0x00000080
1304 #define EN_LmAIPWP 0x00000040
1305 #define EN_LmAIPWD 0x00000020
1306 #define EN_LmAIPWC 0x00000010
1307 #define EN_LmAIPRV2 0x00000008
1308 #define EN_LmAIPRV1 0x00000004
1309 #define EN_LmAIPRV0 0x00000002
1310 #define EN_LmAIPNRML 0x00000001
1311 
1312 #define LmPRIMSTAT0EN_MASK (EN_LmBREAK | \
1313  EN_LmDONE | EN_LmOPENACPT | \
1314  EN_LmOPENRJCT | EN_LmOPENRTRY | \
1315  EN_LmCLOSERV1 | EN_LmCLOSERV0 | \
1316  EN_LmCLOSENORM | EN_LmCLOSECLAF | \
1317  EN_LmBROADRV4 | EN_LmBROADRV3 | \
1318  EN_LmBROADRV2 | EN_LmBROADRV1 | \
1319  EN_LmBROADRV0 | EN_LmBROADRVCH1 | \
1320  EN_LmBROADRVCH0 | EN_LmBROADCH | \
1321  EN_LmAIPRVWP | EN_LmAIPWP | \
1322  EN_LmAIPWD | EN_LmAIPWC | \
1323  EN_LmAIPRV2 | EN_LmAIPRV1 | \
1324  EN_LmAIPRV0 | EN_LmAIPNRML)
1325 
1326 #define LmPRIMSTAT1EN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xE4)
1327 
1328 #define EN_LmXRDY 0x00040000
1329 #define EN_LmSYNCSRST 0x00020000
1330 #define EN_LmSYNC 0x00010000
1331 #define EN_LmXHOLD 0x00008000
1332 #define EN_LmRRDY 0x00004000
1333 #define EN_LmHOLD 0x00002000
1334 #define EN_LmROK 0x00001000
1335 #define EN_LmRIP 0x00000800
1336 #define EN_LmCRBLK 0x00000400
1337 #define EN_LmACK 0x00000200
1338 #define EN_LmNAK 0x00000100
1339 #define EN_LmHARDRST 0x00000080
1340 #define EN_LmERROR 0x00000040
1341 #define EN_LmRERR 0x00000020
1342 #define EN_LmPMREQP 0x00000010
1343 #define EN_LmPMREQS 0x00000008
1344 #define EN_LmPMACK 0x00000004
1345 #define EN_LmPMNAK 0x00000002
1346 #define EN_LmDMAT 0x00000001
1347 
1348 #define LmPRIMSTAT1EN_MASK (EN_LmHARDRST | \
1349  EN_LmSYNCSRST | \
1350  EN_LmPMREQP | EN_LmPMREQS | \
1351  EN_LmPMACK | EN_LmPMNAK)
1352 
1353 #define LmSMSTATE(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xE8)
1354 
1355 #define LmSMSTATEBRK(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xEC)
1356 
1357 #define LmSMDBGCTL(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xF0)
1358 
1359 
1360 /*
1361  * LmSEQ CIO Bus Mode 3 Register.
1362  * Mode 3: Configuration and Setup, IOP Context SCB.
1363  */
1364 #define LmM3SATATIMER(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x48)
1365 
1366 #define LmM3INTVEC0(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x90)
1367 
1368 #define LmM3INTVEC1(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x92)
1369 
1370 #define LmM3INTVEC2(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x94)
1371 
1372 #define LmM3INTVEC3(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x96)
1373 
1374 #define LmM3INTVEC4(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x98)
1375 
1376 #define LmM3INTVEC5(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x9A)
1377 
1378 #define LmM3INTVEC6(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x9C)
1379 
1380 #define LmM3INTVEC7(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0x9E)
1381 
1382 #define LmM3INTVEC8(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xA4)
1383 
1384 #define LmM3INTVEC9(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xA6)
1385 
1386 #define LmM3INTVEC10(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xB0)
1387 
1388 #define LmM3FRMGAP(LinkNum) LmSEQ_PHY_REG(3, LinkNum, 0xB4)
1389 
1390 #define LmBITL_TIMER(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xA2)
1391 
1392 #define LmWWN(LinkNum) LmSEQ_PHY_REG(0, LinkNum, 0xA8)
1393 
1394 
1395 /*
1396  * LmSEQ CIO Bus Mode 5 Registers.
1397  * Mode 5: Phy/OOB Control and Status.
1398  */
1399 #define LmSEQ_OOB_REG(phy_id, reg) LmSEQ_PHY_REG(5, (phy_id), (reg))
1400 
1401 #define OOB_BFLTR 0x100
1402 
1403 #define BFLTR_THR_MASK 0xF0
1404 #define BFLTR_TC_MASK 0x0F
1405 
1406 #define OOB_INIT_MIN 0x102
1407 
1408 #define OOB_INIT_MAX 0x104
1409 
1410 #define OOB_INIT_NEG 0x106
1411 
1412 #define OOB_SAS_MIN 0x108
1413 
1414 #define OOB_SAS_MAX 0x10A
1415 
1416 #define OOB_SAS_NEG 0x10C
1417 
1418 #define OOB_WAKE_MIN 0x10E
1419 
1420 #define OOB_WAKE_MAX 0x110
1421 
1422 #define OOB_WAKE_NEG 0x112
1423 
1424 #define OOB_IDLE_MAX 0x114
1425 
1426 #define OOB_BURST_MAX 0x116
1427 
1428 #define OOB_DATA_KBITS 0x126
1429 
1430 #define OOB_ALIGN_0_DATA 0x12C
1431 
1432 #define OOB_ALIGN_1_DATA 0x130
1433 
1434 #define D10_2_DATA_k 0x00
1435 #define SYNC_DATA_k 0x02
1436 #define ALIGN_1_DATA_k 0x04
1437 #define ALIGN_0_DATA_k 0x08
1438 #define BURST_DATA_k 0x10
1439 
1440 #define OOB_PHY_RESET_COUNT 0x13C
1441 
1442 #define OOB_SIG_GEN 0x140
1443 
1444 #define START_OOB 0x80
1445 #define START_DWS 0x40
1446 #define ALIGN_CNT3 0x30
1447 #define ALIGN_CNT2 0x20
1448 #define ALIGN_CNT1 0x10
1449 #define ALIGN_CNT4 0x00
1450 #define STOP_DWS 0x08
1451 #define SEND_COMSAS 0x04
1452 #define SEND_COMINIT 0x02
1453 #define SEND_COMWAKE 0x01
1454 
1455 #define OOB_XMIT 0x141
1456 
1457 #define TX_ENABLE 0x80
1458 #define XMIT_OOB_BURST 0x10
1459 #define XMIT_D10_2 0x08
1460 #define XMIT_SYNC 0x04
1461 #define XMIT_ALIGN_1 0x02
1462 #define XMIT_ALIGN_0 0x01
1463 
1464 #define FUNCTION_MASK 0x142
1465 
1466 #define SAS_MODE_DIS 0x80
1467 #define SATA_MODE_DIS 0x40
1468 #define SPINUP_HOLD_DIS 0x20
1469 #define HOT_PLUG_DIS 0x10
1470 #define SATA_PS_DIS 0x08
1471 #define FUNCTION_MASK_DEFAULT (SPINUP_HOLD_DIS | SATA_PS_DIS)
1472 
1473 #define OOB_MODE 0x143
1474 
1475 #define SAS_MODE 0x80
1476 #define SATA_MODE 0x40
1477 #define SLOW_CLK 0x20
1478 #define FORCE_XMIT_15 0x08
1479 #define PHY_SPEED_60 0x04
1480 #define PHY_SPEED_30 0x02
1481 #define PHY_SPEED_15 0x01
1482 
1483 #define CURRENT_STATUS 0x144
1484 
1485 #define CURRENT_OOB_DONE 0x80
1486 #define CURRENT_LOSS_OF_SIGNAL 0x40
1487 #define CURRENT_SPINUP_HOLD 0x20
1488 #define CURRENT_HOT_PLUG_CNCT 0x10
1489 #define CURRENT_GTO_TIMEOUT 0x08
1490 #define CURRENT_OOB_TIMEOUT 0x04
1491 #define CURRENT_DEVICE_PRESENT 0x02
1492 #define CURRENT_OOB_ERROR 0x01
1493 
1494 #define CURRENT_OOB1_ERROR (CURRENT_HOT_PLUG_CNCT | \
1495  CURRENT_GTO_TIMEOUT)
1496 
1497 #define CURRENT_OOB2_ERROR (CURRENT_HOT_PLUG_CNCT | \
1498  CURRENT_OOB_ERROR)
1499 
1500 #define DEVICE_ADDED_W_CNT (CURRENT_OOB_DONE | \
1501  CURRENT_HOT_PLUG_CNCT | \
1502  CURRENT_DEVICE_PRESENT)
1503 
1504 #define DEVICE_ADDED_WO_CNT (CURRENT_OOB_DONE | \
1505  CURRENT_DEVICE_PRESENT)
1506 
1507 #define DEVICE_REMOVED CURRENT_LOSS_OF_SIGNAL
1508 
1509 #define CURRENT_PHY_MASK (CURRENT_OOB_DONE | \
1510  CURRENT_LOSS_OF_SIGNAL | \
1511  CURRENT_SPINUP_HOLD | \
1512  CURRENT_HOT_PLUG_CNCT | \
1513  CURRENT_GTO_TIMEOUT | \
1514  CURRENT_DEVICE_PRESENT | \
1515  CURRENT_OOB_ERROR )
1516 
1517 #define CURRENT_ERR_MASK (CURRENT_LOSS_OF_SIGNAL | \
1518  CURRENT_GTO_TIMEOUT | \
1519  CURRENT_OOB_TIMEOUT | \
1520  CURRENT_OOB_ERROR )
1521 
1522 #define SPEED_MASK 0x145
1523 
1524 #define SATA_SPEED_30_DIS 0x10
1525 #define SATA_SPEED_15_DIS 0x08
1526 #define SAS_SPEED_60_DIS 0x04
1527 #define SAS_SPEED_30_DIS 0x02
1528 #define SAS_SPEED_15_DIS 0x01
1529 #define SAS_SPEED_MASK_DEFAULT 0x00
1530 
1531 #define OOB_TIMER_ENABLE 0x14D
1532 
1533 #define HOT_PLUG_EN 0x80
1534 #define RCD_EN 0x40
1535 #define COMTIMER_EN 0x20
1536 #define SNTT_EN 0x10
1537 #define SNLT_EN 0x04
1538 #define SNWT_EN 0x02
1539 #define ALIGN_EN 0x01
1540 
1541 #define OOB_STATUS 0x14E
1542 
1543 #define OOB_DONE 0x80
1544 #define LOSS_OF_SIGNAL 0x40 /* ro */
1545 #define SPINUP_HOLD 0x20
1546 #define HOT_PLUG_CNCT 0x10 /* ro */
1547 #define GTO_TIMEOUT 0x08 /* ro */
1548 #define OOB_TIMEOUT 0x04 /* ro */
1549 #define DEVICE_PRESENT 0x02 /* ro */
1550 #define OOB_ERROR 0x01 /* ro */
1551 
1552 #define OOB_STATUS_ERROR_MASK (LOSS_OF_SIGNAL | GTO_TIMEOUT | \
1553  OOB_TIMEOUT | OOB_ERROR)
1554 
1555 #define OOB_STATUS_CLEAR 0x14F
1556 
1557 #define OOB_DONE_CLR 0x80
1558 #define LOSS_OF_SIGNAL_CLR 0x40
1559 #define SPINUP_HOLD_CLR 0x20
1560 #define HOT_PLUG_CNCT_CLR 0x10
1561 #define GTO_TIMEOUT_CLR 0x08
1562 #define OOB_TIMEOUT_CLR 0x04
1563 #define OOB_ERROR_CLR 0x01
1564 
1565 #define HOT_PLUG_DELAY 0x150
1566 /* In 5 ms units. 20 = 100 ms. */
1567 #define HOTPLUG_DELAY_TIMEOUT 20
1568 
1569 
1570 #define INT_ENABLE_2 0x15A
1571 
1572 #define OOB_DONE_EN 0x80
1573 #define LOSS_OF_SIGNAL_EN 0x40
1574 #define SPINUP_HOLD_EN 0x20
1575 #define HOT_PLUG_CNCT_EN 0x10
1576 #define GTO_TIMEOUT_EN 0x08
1577 #define OOB_TIMEOUT_EN 0x04
1578 #define DEVICE_PRESENT_EN 0x02
1579 #define OOB_ERROR_EN 0x01
1580 
1581 #define PHY_CONTROL_0 0x160
1582 
1583 #define PHY_LOWPWREN_TX 0x80
1584 #define PHY_LOWPWREN_RX 0x40
1585 #define SPARE_REG_160_B5 0x20
1586 #define OFFSET_CANCEL_RX 0x10
1587 
1588 /* bits 3:2 */
1589 #define PHY_RXCOMCENTER_60V 0x00
1590 #define PHY_RXCOMCENTER_70V 0x04
1591 #define PHY_RXCOMCENTER_80V 0x08
1592 #define PHY_RXCOMCENTER_90V 0x0C
1593 #define PHY_RXCOMCENTER_MASK 0x0C
1594 
1595 #define PHY_RESET 0x02
1596 #define SAS_DEFAULT_SEL 0x01
1597 
1598 #define PHY_CONTROL_1 0x161
1599 
1600 /* bits 2:0 */
1601 #define SATA_PHY_DETLEVEL_50mv 0x00
1602 #define SATA_PHY_DETLEVEL_75mv 0x01
1603 #define SATA_PHY_DETLEVEL_100mv 0x02
1604 #define SATA_PHY_DETLEVEL_125mv 0x03
1605 #define SATA_PHY_DETLEVEL_150mv 0x04
1606 #define SATA_PHY_DETLEVEL_175mv 0x05
1607 #define SATA_PHY_DETLEVEL_200mv 0x06
1608 #define SATA_PHY_DETLEVEL_225mv 0x07
1609 #define SATA_PHY_DETLEVEL_MASK 0x07
1610 
1611 /* bits 5:3 */
1612 #define SAS_PHY_DETLEVEL_50mv 0x00
1613 #define SAS_PHY_DETLEVEL_75mv 0x08
1614 #define SAS_PHY_DETLEVEL_100mv 0x10
1615 #define SAS_PHY_DETLEVEL_125mv 0x11
1616 #define SAS_PHY_DETLEVEL_150mv 0x20
1617 #define SAS_PHY_DETLEVEL_175mv 0x21
1618 #define SAS_PHY_DETLEVEL_200mv 0x30
1619 #define SAS_PHY_DETLEVEL_225mv 0x31
1620 #define SAS_PHY_DETLEVEL_MASK 0x38
1621 
1622 #define PHY_CONTROL_2 0x162
1623 
1624 /* bits 7:5 */
1625 #define SATA_PHY_DRV_400mv 0x00
1626 #define SATA_PHY_DRV_450mv 0x20
1627 #define SATA_PHY_DRV_500mv 0x40
1628 #define SATA_PHY_DRV_550mv 0x60
1629 #define SATA_PHY_DRV_600mv 0x80
1630 #define SATA_PHY_DRV_650mv 0xA0
1631 #define SATA_PHY_DRV_725mv 0xC0
1632 #define SATA_PHY_DRV_800mv 0xE0
1633 #define SATA_PHY_DRV_MASK 0xE0
1634 
1635 /* bits 4:3 */
1636 #define SATA_PREEMP_0 0x00
1637 #define SATA_PREEMP_1 0x08
1638 #define SATA_PREEMP_2 0x10
1639 #define SATA_PREEMP_3 0x18
1640 #define SATA_PREEMP_MASK 0x18
1641 
1642 #define SATA_CMSH1P5 0x04
1643 
1644 /* bits 1:0 */
1645 #define SATA_SLEW_0 0x00
1646 #define SATA_SLEW_1 0x01
1647 #define SATA_SLEW_2 0x02
1648 #define SATA_SLEW_3 0x03
1649 #define SATA_SLEW_MASK 0x03
1650 
1651 #define PHY_CONTROL_3 0x163
1652 
1653 /* bits 7:5 */
1654 #define SAS_PHY_DRV_400mv 0x00
1655 #define SAS_PHY_DRV_450mv 0x20
1656 #define SAS_PHY_DRV_500mv 0x40
1657 #define SAS_PHY_DRV_550mv 0x60
1658 #define SAS_PHY_DRV_600mv 0x80
1659 #define SAS_PHY_DRV_650mv 0xA0
1660 #define SAS_PHY_DRV_725mv 0xC0
1661 #define SAS_PHY_DRV_800mv 0xE0
1662 #define SAS_PHY_DRV_MASK 0xE0
1663 
1664 /* bits 4:3 */
1665 #define SAS_PREEMP_0 0x00
1666 #define SAS_PREEMP_1 0x08
1667 #define SAS_PREEMP_2 0x10
1668 #define SAS_PREEMP_3 0x18
1669 #define SAS_PREEMP_MASK 0x18
1670 
1671 #define SAS_CMSH1P5 0x04
1672 
1673 /* bits 1:0 */
1674 #define SAS_SLEW_0 0x00
1675 #define SAS_SLEW_1 0x01
1676 #define SAS_SLEW_2 0x02
1677 #define SAS_SLEW_3 0x03
1678 #define SAS_SLEW_MASK 0x03
1679 
1680 #define PHY_CONTROL_4 0x168
1681 
1682 #define PHY_DONE_CAL_TX 0x80
1683 #define PHY_DONE_CAL_RX 0x40
1684 #define RX_TERM_LOAD_DIS 0x20
1685 #define TX_TERM_LOAD_DIS 0x10
1686 #define AUTO_TERM_CAL_DIS 0x08
1687 #define PHY_SIGDET_FLTR_EN 0x04
1688 #define OSC_FREQ 0x02
1689 #define PHY_START_CAL 0x01
1690 
1691 /*
1692  * HST_PCIX2 Registers, Address Range: (0x00-0xFC)
1693  */
1694 #define PCIX_REG_BASE_ADR 0xB8040000
1695 
1696 #define PCIC_VENDOR_ID 0x00
1697 
1698 #define PCIC_DEVICE_ID 0x02
1699 
1700 #define PCIC_COMMAND 0x04
1701 
1702 #define INT_DIS 0x0400
1703 #define FBB_EN 0x0200 /* ro */
1704 #define SERR_EN 0x0100
1705 #define STEP_EN 0x0080 /* ro */
1706 #define PERR_EN 0x0040
1707 #define VGA_EN 0x0020 /* ro */
1708 #define MWI_EN 0x0010
1709 #define SPC_EN 0x0008
1710 #define MST_EN 0x0004
1711 #define MEM_EN 0x0002
1712 #define IO_EN 0x0001
1713 
1714 #define PCIC_STATUS 0x06
1715 
1716 #define PERR_DET 0x8000
1717 #define SERR_GEN 0x4000
1718 #define MABT_DET 0x2000
1719 #define TABT_DET 0x1000
1720 #define TABT_GEN 0x0800
1721 #define DPERR_DET 0x0100
1722 #define CAP_LIST 0x0010
1723 #define INT_STAT 0x0008
1724 
1725 #define PCIC_DEVREV_ID 0x08
1726 
1727 #define PCIC_CLASS_CODE 0x09
1728 
1729 #define PCIC_CACHELINE_SIZE 0x0C
1730 
1731 #define PCIC_MBAR0 0x10
1732 
1733 #define PCIC_MBAR0_OFFSET 0
1734 
1735 #define PCIC_MBAR1 0x18
1736 
1737 #define PCIC_MBAR1_OFFSET 2
1738 
1739 #define PCIC_IOBAR 0x20
1740 
1741 #define PCIC_IOBAR_OFFSET 4
1742 
1743 #define PCIC_SUBVENDOR_ID 0x2C
1744 
1745 #define PCIC_SUBSYTEM_ID 0x2E
1746 
1747 #define PCIX_STATUS 0x44
1748 #define RCV_SCE 0x20000000
1749 #define UNEXP_SC 0x00080000
1750 #define SC_DISCARD 0x00040000
1751 
1752 #define ECC_CTRL_STAT 0x48
1753 #define UNCOR_ECCERR 0x00000008
1754 
1755 #define PCIC_PM_CSR 0x5C
1756 
1757 #define PWR_STATE_D0 0
1758 #define PWR_STATE_D1 1 /* not supported */
1759 #define PWR_STATE_D2 2 /* not supported */
1760 #define PWR_STATE_D3 3
1761 
1762 #define PCIC_BASE1 0x6C /* internal use only */
1763 
1764 #define BASE1_RSVD 0xFFFFFFF8
1765 
1766 #define PCIC_BASEA 0x70 /* internal use only */
1767 
1768 #define BASEA_RSVD 0xFFFFFFC0
1769 #define BASEA_START 0
1770 
1771 #define PCIC_BASEB 0x74 /* internal use only */
1772 
1773 #define BASEB_RSVD 0xFFFFFF80
1774 #define BASEB_IOMAP_MASK 0x7F
1775 #define BASEB_START 0x80
1776 
1777 #define PCIC_BASEC 0x78 /* internal use only */
1778 
1779 #define BASEC_RSVD 0xFFFFFFFC
1780 #define BASEC_MASK 0x03
1781 #define BASEC_START 0x58
1782 
1783 #define PCIC_MBAR_KEY 0x7C /* internal use only */
1784 
1785 #define MBAR_KEY_MASK 0xFFFFFFFF
1786 
1787 #define PCIC_HSTPCIX_CNTRL 0xA0
1788 
1789 #define REWIND_DIS 0x0800
1790 #define SC_TMR_DIS 0x04000000
1791 
1792 #define PCIC_MBAR0_MASK 0xA8
1793 #define PCIC_MBAR0_SIZE_MASK 0x1FFFE000
1794 #define PCIC_MBAR0_SIZE_SHIFT 13
1795 #define PCIC_MBAR0_SIZE(val) \
1796  (((val) & PCIC_MBAR0_SIZE_MASK) >> PCIC_MBAR0_SIZE_SHIFT)
1797 
1798 #define PCIC_FLASH_MBAR 0xB8
1799 
1800 #define PCIC_INTRPT_STAT 0xD4
1801 
1802 #define PCIC_TP_CTRL 0xFC
1803 
1804 /*
1805  * EXSI Registers, Address Range: (0x00-0xFC)
1806  */
1807 #define EXSI_REG_BASE_ADR REG_BASE_ADDR_EXSI
1808 
1809 #define EXSICNFGR (EXSI_REG_BASE_ADR + 0x00)
1810 
1811 #define OCMINITIALIZED 0x80000000
1812 #define ASIEN 0x00400000
1813 #define HCMODE 0x00200000
1814 #define PCIDEF 0x00100000
1815 #define COMSTOCK 0x00080000
1816 #define SEEPROMEND 0x00040000
1817 #define MSTTIMEN 0x00020000
1818 #define XREGEX 0x00000200
1819 #define NVRAMW 0x00000100
1820 #define NVRAMEX 0x00000080
1821 #define SRAMW 0x00000040
1822 #define SRAMEX 0x00000020
1823 #define FLASHW 0x00000010
1824 #define FLASHEX 0x00000008
1825 #define SEEPROMCFG 0x00000004
1826 #define SEEPROMTYP 0x00000002
1827 #define SEEPROMEX 0x00000001
1828 
1829 
1830 #define EXSICNTRLR (EXSI_REG_BASE_ADR + 0x04)
1831 
1832 #define MODINT_EN 0x00000001
1833 
1834 
1835 #define PMSTATR (EXSI_REG_BASE_ADR + 0x10)
1836 
1837 #define FLASHRST 0x00000002
1838 #define FLASHRDY 0x00000001
1839 
1840 
1841 #define FLCNFGR (EXSI_REG_BASE_ADR + 0x14)
1842 
1843 #define FLWEH_MASK 0x30000000
1844 #define FLWESU_MASK 0x0C000000
1845 #define FLWEPW_MASK 0x03F00000
1846 #define FLOEH_MASK 0x000C0000
1847 #define FLOESU_MASK 0x00030000
1848 #define FLOEPW_MASK 0x0000FC00
1849 #define FLCSH_MASK 0x00000300
1850 #define FLCSSU_MASK 0x000000C0
1851 #define FLCSPW_MASK 0x0000003F
1852 
1853 #define SRCNFGR (EXSI_REG_BASE_ADR + 0x18)
1854 
1855 #define SRWEH_MASK 0x30000000
1856 #define SRWESU_MASK 0x0C000000
1857 #define SRWEPW_MASK 0x03F00000
1858 
1859 #define SROEH_MASK 0x000C0000
1860 #define SROESU_MASK 0x00030000
1861 #define SROEPW_MASK 0x0000FC00
1862 #define SRCSH_MASK 0x00000300
1863 #define SRCSSU_MASK 0x000000C0
1864 #define SRCSPW_MASK 0x0000003F
1865 
1866 #define NVCNFGR (EXSI_REG_BASE_ADR + 0x1C)
1867 
1868 #define NVWEH_MASK 0x30000000
1869 #define NVWESU_MASK 0x0C000000
1870 #define NVWEPW_MASK 0x03F00000
1871 #define NVOEH_MASK 0x000C0000
1872 #define NVOESU_MASK 0x00030000
1873 #define NVOEPW_MASK 0x0000FC00
1874 #define NVCSH_MASK 0x00000300
1875 #define NVCSSU_MASK 0x000000C0
1876 #define NVCSPW_MASK 0x0000003F
1877 
1878 #define XRCNFGR (EXSI_REG_BASE_ADR + 0x20)
1879 
1880 #define XRWEH_MASK 0x30000000
1881 #define XRWESU_MASK 0x0C000000
1882 #define XRWEPW_MASK 0x03F00000
1883 #define XROEH_MASK 0x000C0000
1884 #define XROESU_MASK 0x00030000
1885 #define XROEPW_MASK 0x0000FC00
1886 #define XRCSH_MASK 0x00000300
1887 #define XRCSSU_MASK 0x000000C0
1888 #define XRCSPW_MASK 0x0000003F
1889 
1890 #define XREGADDR (EXSI_REG_BASE_ADR + 0x24)
1891 
1892 #define XRADDRINCEN 0x80000000
1893 #define XREGADD_MASK 0x007FFFFF
1894 
1895 
1896 #define XREGDATAR (EXSI_REG_BASE_ADR + 0x28)
1897 
1898 #define XREGDATA_MASK 0x0000FFFF
1899 
1900 #define GPIOOER (EXSI_REG_BASE_ADR + 0x40)
1901 
1902 #define GPIOODENR (EXSI_REG_BASE_ADR + 0x44)
1903 
1904 #define GPIOINVR (EXSI_REG_BASE_ADR + 0x48)
1905 
1906 #define GPIODATAOR (EXSI_REG_BASE_ADR + 0x4C)
1907 
1908 #define GPIODATAIR (EXSI_REG_BASE_ADR + 0x50)
1909 
1910 #define GPIOCNFGR (EXSI_REG_BASE_ADR + 0x54)
1911 
1912 #define GPIO_EXTSRC 0x00000001
1913 
1914 #define SCNTRLR (EXSI_REG_BASE_ADR + 0xA0)
1915 
1916 #define SXFERDONE 0x00000100
1917 #define SXFERCNT_MASK 0x000000E0
1918 #define SCMDTYP_MASK 0x0000001C
1919 #define SXFERSTART 0x00000002
1920 #define SXFEREN 0x00000001
1921 
1922 #define SRATER (EXSI_REG_BASE_ADR + 0xA4)
1923 
1924 #define SADDRR (EXSI_REG_BASE_ADR + 0xA8)
1925 
1926 #define SADDR_MASK 0x0000FFFF
1927 
1928 #define SDATAOR (EXSI_REG_BASE_ADR + 0xAC)
1929 
1930 #define SDATAOR0 (EXSI_REG_BASE_ADR + 0xAC)
1931 #define SDATAOR1 (EXSI_REG_BASE_ADR + 0xAD)
1932 #define SDATAOR2 (EXSI_REG_BASE_ADR + 0xAE)
1933 #define SDATAOR3 (EXSI_REG_BASE_ADR + 0xAF)
1934 
1935 #define SDATAIR (EXSI_REG_BASE_ADR + 0xB0)
1936 
1937 #define SDATAIR0 (EXSI_REG_BASE_ADR + 0xB0)
1938 #define SDATAIR1 (EXSI_REG_BASE_ADR + 0xB1)
1939 #define SDATAIR2 (EXSI_REG_BASE_ADR + 0xB2)
1940 #define SDATAIR3 (EXSI_REG_BASE_ADR + 0xB3)
1941 
1942 #define ASISTAT0R (EXSI_REG_BASE_ADR + 0xD0)
1943 #define ASIFMTERR 0x00000400
1944 #define ASISEECHKERR 0x00000200
1945 #define ASIERR 0x00000100
1946 
1947 #define ASISTAT1R (EXSI_REG_BASE_ADR + 0xD4)
1948 #define CHECKSUM_MASK 0x0000FFFF
1949 
1950 #define ASIERRADDR (EXSI_REG_BASE_ADR + 0xD8)
1951 #define ASIERRDATAR (EXSI_REG_BASE_ADR + 0xDC)
1952 #define ASIERRSTATR (EXSI_REG_BASE_ADR + 0xE0)
1953 #define CPI2ASIBYTECNT_MASK 0x00070000
1954 #define CPI2ASIBYTEEN_MASK 0x0000F000
1955 #define CPI2ASITARGERR_MASK 0x00000F00
1956 #define CPI2ASITARGMID_MASK 0x000000F0
1957 #define CPI2ASIMSTERR_MASK 0x0000000F
1958 
1959 /*
1960  * XSRAM, External SRAM (DWord and any BE pattern accessible)
1961  */
1962 #define XSRAM_REG_BASE_ADDR 0xB8100000
1963 #define XSRAM_SIZE 0x100000
1964 
1965 /*
1966  * NVRAM Registers, Address Range: (0x00000 - 0x3FFFF).
1967  */
1968 #define NVRAM_REG_BASE_ADR 0xBF800000
1969 #define NVRAM_MAX_BASE_ADR 0x003FFFFF
1970 
1971 /* OCM base address */
1972 #define OCM_BASE_ADDR 0xA0000000
1973 #define OCM_MAX_SIZE 0x20000
1974 
1975 /*
1976  * Sequencers (Central and Link) Scratch RAM page definitions.
1977  */
1978 
1979 /*
1980  * The Central Management Sequencer (CSEQ) Scratch Memory is a 1024
1981  * byte memory. It is dword accessible and has byte parity
1982  * protection. The CSEQ accesses it in 32 byte windows, either as mode
1983  * dependent or mode independent memory. Each mode has 96 bytes,
1984  * (three 32 byte pages 0-2, not contiguous), leaving 128 bytes of
1985  * Mode Independent memory (four 32 byte pages 3-7). Note that mode
1986  * dependent scratch memory, Mode 8, page 0-3 overlaps mode
1987  * independent scratch memory, pages 0-3.
1988  * - 896 bytes of mode dependent scratch, 96 bytes per Modes 0-7, and
1989  * 128 bytes in mode 8,
1990  * - 259 bytes of mode independent scratch, common to modes 0-15.
1991  *
1992  * Sequencer scratch RAM is 1024 bytes. This scratch memory is
1993  * divided into mode dependent and mode independent scratch with this
1994  * memory further subdivided into pages of size 32 bytes. There are 5
1995  * pages (160 bytes) of mode independent scratch and 3 pages of
1996  * dependent scratch memory for modes 0-7 (768 bytes). Mode 8 pages
1997  * 0-2 dependent scratch overlap with pages 0-2 of mode independent
1998  * scratch memory.
1999  *
2000  * The host accesses this scratch in a different manner from the
2001  * central sequencer. The sequencer has to use CSEQ registers CSCRPAGE
2002  * and CMnSCRPAGE to access the scratch memory. A flat mapping of the
2003  * scratch memory is available for software convenience and to prevent
2004  * corruption while the sequencer is running. This memory is mapped
2005  * onto addresses 800h - BFFh, total of 400h bytes.
2006  *
2007  * These addresses are mapped as follows:
2008  *
2009  * 800h-83Fh Mode Dependent Scratch Mode 0 Pages 0-1
2010  * 840h-87Fh Mode Dependent Scratch Mode 1 Pages 0-1
2011  * 880h-8BFh Mode Dependent Scratch Mode 2 Pages 0-1
2012  * 8C0h-8FFh Mode Dependent Scratch Mode 3 Pages 0-1
2013  * 900h-93Fh Mode Dependent Scratch Mode 4 Pages 0-1
2014  * 940h-97Fh Mode Dependent Scratch Mode 5 Pages 0-1
2015  * 980h-9BFh Mode Dependent Scratch Mode 6 Pages 0-1
2016  * 9C0h-9FFh Mode Dependent Scratch Mode 7 Pages 0-1
2017  * A00h-A5Fh Mode Dependent Scratch Mode 8 Pages 0-2
2018  * Mode Independent Scratch Pages 0-2
2019  * A60h-A7Fh Mode Dependent Scratch Mode 8 Page 3
2020  * Mode Independent Scratch Page 3
2021  * A80h-AFFh Mode Independent Scratch Pages 4-7
2022  * B00h-B1Fh Mode Dependent Scratch Mode 0 Page 2
2023  * B20h-B3Fh Mode Dependent Scratch Mode 1 Page 2
2024  * B40h-B5Fh Mode Dependent Scratch Mode 2 Page 2
2025  * B60h-B7Fh Mode Dependent Scratch Mode 3 Page 2
2026  * B80h-B9Fh Mode Dependent Scratch Mode 4 Page 2
2027  * BA0h-BBFh Mode Dependent Scratch Mode 5 Page 2
2028  * BC0h-BDFh Mode Dependent Scratch Mode 6 Page 2
2029  * BE0h-BFFh Mode Dependent Scratch Mode 7 Page 2
2030  */
2031 
2032 /* General macros */
2033 #define CSEQ_PAGE_SIZE 32 /* Scratch page size (in bytes) */
2034 
2035 /* All macros start with offsets from base + 0x800 (CMAPPEDSCR).
2036  * Mode dependent scratch page 0, mode 0.
2037  * For modes 1-7 you have to do arithmetic. */
2038 #define CSEQ_LRM_SAVE_SINDEX (CMAPPEDSCR + 0x0000)
2039 #define CSEQ_LRM_SAVE_SCBPTR (CMAPPEDSCR + 0x0002)
2040 #define CSEQ_Q_LINK_HEAD (CMAPPEDSCR + 0x0004)
2041 #define CSEQ_Q_LINK_TAIL (CMAPPEDSCR + 0x0006)
2042 #define CSEQ_LRM_SAVE_SCRPAGE (CMAPPEDSCR + 0x0008)
2043 
2044 /* Mode dependent scratch page 0 mode 8 macros. */
2045 #define CSEQ_RET_ADDR (CMAPPEDSCR + 0x0200)
2046 #define CSEQ_RET_SCBPTR (CMAPPEDSCR + 0x0202)
2047 #define CSEQ_SAVE_SCBPTR (CMAPPEDSCR + 0x0204)
2048 #define CSEQ_EMPTY_TRANS_CTX (CMAPPEDSCR + 0x0206)
2049 #define CSEQ_RESP_LEN (CMAPPEDSCR + 0x0208)
2050 #define CSEQ_TMF_SCBPTR (CMAPPEDSCR + 0x020A)
2051 #define CSEQ_GLOBAL_PREV_SCB (CMAPPEDSCR + 0x020C)
2052 #define CSEQ_GLOBAL_HEAD (CMAPPEDSCR + 0x020E)
2053 #define CSEQ_CLEAR_LU_HEAD (CMAPPEDSCR + 0x0210)
2054 #define CSEQ_TMF_OPCODE (CMAPPEDSCR + 0x0212)
2055 #define CSEQ_SCRATCH_FLAGS (CMAPPEDSCR + 0x0213)
2056 #define CSEQ_HSB_SITE (CMAPPEDSCR + 0x021A)
2057 #define CSEQ_FIRST_INV_SCB_SITE (CMAPPEDSCR + 0x021C)
2058 #define CSEQ_FIRST_INV_DDB_SITE (CMAPPEDSCR + 0x021E)
2059 
2060 /* Mode dependent scratch page 1 mode 8 macros. */
2061 #define CSEQ_LUN_TO_CLEAR (CMAPPEDSCR + 0x0220)
2062 #define CSEQ_LUN_TO_CHECK (CMAPPEDSCR + 0x0228)
2063 
2064 /* Mode dependent scratch page 2 mode 8 macros */
2065 #define CSEQ_HQ_NEW_POINTER (CMAPPEDSCR + 0x0240)
2066 #define CSEQ_HQ_DONE_BASE (CMAPPEDSCR + 0x0248)
2067 #define CSEQ_HQ_DONE_POINTER (CMAPPEDSCR + 0x0250)
2068 #define CSEQ_HQ_DONE_PASS (CMAPPEDSCR + 0x0254)
2069 
2070 /* Mode independent scratch page 4 macros. */
2071 #define CSEQ_Q_EXE_HEAD (CMAPPEDSCR + 0x0280)
2072 #define CSEQ_Q_EXE_TAIL (CMAPPEDSCR + 0x0282)
2073 #define CSEQ_Q_DONE_HEAD (CMAPPEDSCR + 0x0284)
2074 #define CSEQ_Q_DONE_TAIL (CMAPPEDSCR + 0x0286)
2075 #define CSEQ_Q_SEND_HEAD (CMAPPEDSCR + 0x0288)
2076 #define CSEQ_Q_SEND_TAIL (CMAPPEDSCR + 0x028A)
2077 #define CSEQ_Q_DMA2CHIM_HEAD (CMAPPEDSCR + 0x028C)
2078 #define CSEQ_Q_DMA2CHIM_TAIL (CMAPPEDSCR + 0x028E)
2079 #define CSEQ_Q_COPY_HEAD (CMAPPEDSCR + 0x0290)
2080 #define CSEQ_Q_COPY_TAIL (CMAPPEDSCR + 0x0292)
2081 #define CSEQ_REG0 (CMAPPEDSCR + 0x0294)
2082 #define CSEQ_REG1 (CMAPPEDSCR + 0x0296)
2083 #define CSEQ_REG2 (CMAPPEDSCR + 0x0298)
2084 #define CSEQ_LINK_CTL_Q_MAP (CMAPPEDSCR + 0x029C)
2085 #define CSEQ_MAX_CSEQ_MODE (CMAPPEDSCR + 0x029D)
2086 #define CSEQ_FREE_LIST_HACK_COUNT (CMAPPEDSCR + 0x029E)
2087 
2088 /* Mode independent scratch page 5 macros. */
2089 #define CSEQ_EST_NEXUS_REQ_QUEUE (CMAPPEDSCR + 0x02A0)
2090 #define CSEQ_EST_NEXUS_REQ_COUNT (CMAPPEDSCR + 0x02A8)
2091 #define CSEQ_Q_EST_NEXUS_HEAD (CMAPPEDSCR + 0x02B0)
2092 #define CSEQ_Q_EST_NEXUS_TAIL (CMAPPEDSCR + 0x02B2)
2093 #define CSEQ_NEED_EST_NEXUS_SCB (CMAPPEDSCR + 0x02B4)
2094 #define CSEQ_EST_NEXUS_REQ_HEAD (CMAPPEDSCR + 0x02B6)
2095 #define CSEQ_EST_NEXUS_REQ_TAIL (CMAPPEDSCR + 0x02B7)
2096 #define CSEQ_EST_NEXUS_SCB_OFFSET (CMAPPEDSCR + 0x02B8)
2097 
2098 /* Mode independent scratch page 6 macros. */
2099 #define CSEQ_INT_ROUT_RET_ADDR0 (CMAPPEDSCR + 0x02C0)
2100 #define CSEQ_INT_ROUT_RET_ADDR1 (CMAPPEDSCR + 0x02C2)
2101 #define CSEQ_INT_ROUT_SCBPTR (CMAPPEDSCR + 0x02C4)
2102 #define CSEQ_INT_ROUT_MODE (CMAPPEDSCR + 0x02C6)
2103 #define CSEQ_ISR_SCRATCH_FLAGS (CMAPPEDSCR + 0x02C7)
2104 #define CSEQ_ISR_SAVE_SINDEX (CMAPPEDSCR + 0x02C8)
2105 #define CSEQ_ISR_SAVE_DINDEX (CMAPPEDSCR + 0x02CA)
2106 #define CSEQ_Q_MONIRTT_HEAD (CMAPPEDSCR + 0x02D0)
2107 #define CSEQ_Q_MONIRTT_TAIL (CMAPPEDSCR + 0x02D2)
2108 #define CSEQ_FREE_SCB_MASK (CMAPPEDSCR + 0x02D5)
2109 #define CSEQ_BUILTIN_FREE_SCB_HEAD (CMAPPEDSCR + 0x02D6)
2110 #define CSEQ_BUILTIN_FREE_SCB_TAIL (CMAPPEDSCR + 0x02D8)
2111 #define CSEQ_EXTENDED_FREE_SCB_HEAD (CMAPPEDSCR + 0x02DA)
2112 #define CSEQ_EXTENDED_FREE_SCB_TAIL (CMAPPEDSCR + 0x02DC)
2113 
2114 /* Mode independent scratch page 7 macros. */
2115 #define CSEQ_EMPTY_REQ_QUEUE (CMAPPEDSCR + 0x02E0)
2116 #define CSEQ_EMPTY_REQ_COUNT (CMAPPEDSCR + 0x02E8)
2117 #define CSEQ_Q_EMPTY_HEAD (CMAPPEDSCR + 0x02F0)
2118 #define CSEQ_Q_EMPTY_TAIL (CMAPPEDSCR + 0x02F2)
2119 #define CSEQ_NEED_EMPTY_SCB (CMAPPEDSCR + 0x02F4)
2120 #define CSEQ_EMPTY_REQ_HEAD (CMAPPEDSCR + 0x02F6)
2121 #define CSEQ_EMPTY_REQ_TAIL (CMAPPEDSCR + 0x02F7)
2122 #define CSEQ_EMPTY_SCB_OFFSET (CMAPPEDSCR + 0x02F8)
2123 #define CSEQ_PRIMITIVE_DATA (CMAPPEDSCR + 0x02FA)
2124 #define CSEQ_TIMEOUT_CONST (CMAPPEDSCR + 0x02FC)
2125 
2126 /***************************************************************************
2127 * Link m Sequencer scratch RAM is 512 bytes.
2128 * This scratch memory is divided into mode dependent and mode
2129 * independent scratch with this memory further subdivided into
2130 * pages of size 32 bytes. There are 4 pages (128 bytes) of
2131 * mode independent scratch and 4 pages of dependent scratch
2132 * memory for modes 0-2 (384 bytes).
2133 *
2134 * The host accesses this scratch in a different manner from the
2135 * link sequencer. The sequencer has to use LSEQ registers
2136 * LmSCRPAGE and LmMnSCRPAGE to access the scratch memory. A flat
2137 * mapping of the scratch memory is available for software
2138 * convenience and to prevent corruption while the sequencer is
2139 * running. This memory is mapped onto addresses 800h - 9FFh.
2140 *
2141 * These addresses are mapped as follows:
2142 *
2143 * 800h-85Fh Mode Dependent Scratch Mode 0 Pages 0-2
2144 * 860h-87Fh Mode Dependent Scratch Mode 0 Page 3
2145 * Mode Dependent Scratch Mode 5 Page 0
2146 * 880h-8DFh Mode Dependent Scratch Mode 1 Pages 0-2
2147 * 8E0h-8FFh Mode Dependent Scratch Mode 1 Page 3
2148 * Mode Dependent Scratch Mode 5 Page 1
2149 * 900h-95Fh Mode Dependent Scratch Mode 2 Pages 0-2
2150 * 960h-97Fh Mode Dependent Scratch Mode 2 Page 3
2151 * Mode Dependent Scratch Mode 5 Page 2
2152 * 980h-9DFh Mode Independent Scratch Pages 0-3
2153 * 9E0h-9FFh Mode Independent Scratch Page 3
2154 * Mode Dependent Scratch Mode 5 Page 3
2155 *
2156 ****************************************************************************/
2157 /* General macros */
2158 #define LSEQ_MODE_SCRATCH_SIZE 0x80 /* Size of scratch RAM per mode */
2159 #define LSEQ_PAGE_SIZE 0x20 /* Scratch page size (in bytes) */
2160 #define LSEQ_MODE5_PAGE0_OFFSET 0x60
2161 
2162 /* Common mode dependent scratch page 0 macros for modes 0,1,2, and 5 */
2163 /* Indexed using LSEQ_MODE_SCRATCH_SIZE * mode, for modes 0,1,2. */
2164 #define LmSEQ_RET_ADDR(LinkNum) (LmSCRATCH(LinkNum) + 0x0000)
2165 #define LmSEQ_REG0_MODE(LinkNum) (LmSCRATCH(LinkNum) + 0x0002)
2166 #define LmSEQ_MODE_FLAGS(LinkNum) (LmSCRATCH(LinkNum) + 0x0004)
2167 
2168 /* Mode flag macros (byte 0) */
2169 #define SAS_SAVECTX_OCCURRED 0x80
2170 #define SAS_OOBSVC_OCCURRED 0x40
2171 #define SAS_OOB_DEVICE_PRESENT 0x20
2172 #define SAS_CFGHDR_OCCURRED 0x10
2173 #define SAS_RCV_INTS_ARE_DISABLED 0x08
2174 #define SAS_OOB_HOT_PLUG_CNCT 0x04
2175 #define SAS_AWAIT_OPEN_CONNECTION 0x02
2176 #define SAS_CFGCMPLT_OCCURRED 0x01
2177 
2178 /* Mode flag macros (byte 1) */
2179 #define SAS_RLSSCB_OCCURRED 0x80
2180 #define SAS_FORCED_HEADER_MISS 0x40
2181 
2182 #define LmSEQ_RET_ADDR2(LinkNum) (LmSCRATCH(LinkNum) + 0x0006)
2183 #define LmSEQ_RET_ADDR1(LinkNum) (LmSCRATCH(LinkNum) + 0x0008)
2184 #define LmSEQ_OPCODE_TO_CSEQ(LinkNum) (LmSCRATCH(LinkNum) + 0x000B)
2185 #define LmSEQ_DATA_TO_CSEQ(LinkNum) (LmSCRATCH(LinkNum) + 0x000C)
2186 
2187 /* Mode dependent scratch page 0 macros for mode 0 (non-common) */
2188 /* Absolute offsets */
2189 #define LmSEQ_FIRST_INV_DDB_SITE(LinkNum) (LmSCRATCH(LinkNum) + 0x000E)
2190 #define LmSEQ_EMPTY_TRANS_CTX(LinkNum) (LmSCRATCH(LinkNum) + 0x0010)
2191 #define LmSEQ_RESP_LEN(LinkNum) (LmSCRATCH(LinkNum) + 0x0012)
2192 #define LmSEQ_FIRST_INV_SCB_SITE(LinkNum) (LmSCRATCH(LinkNum) + 0x0014)
2193 #define LmSEQ_INTEN_SAVE(LinkNum) (LmSCRATCH(LinkNum) + 0x0016)
2194 #define LmSEQ_LINK_RST_FRM_LEN(LinkNum) (LmSCRATCH(LinkNum) + 0x001A)
2195 #define LmSEQ_LINK_RST_PROTOCOL(LinkNum) (LmSCRATCH(LinkNum) + 0x001B)
2196 #define LmSEQ_RESP_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x001C)
2197 #define LmSEQ_LAST_LOADED_SGE(LinkNum) (LmSCRATCH(LinkNum) + 0x001D)
2198 #define LmSEQ_SAVE_SCBPTR(LinkNum) (LmSCRATCH(LinkNum) + 0x001E)
2199 
2200 /* Mode dependent scratch page 0 macros for mode 1 (non-common) */
2201 /* Absolute offsets */
2202 #define LmSEQ_Q_XMIT_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x008E)
2203 #define LmSEQ_M1_EMPTY_TRANS_CTX(LinkNum) (LmSCRATCH(LinkNum) + 0x0090)
2204 #define LmSEQ_INI_CONN_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x0092)
2205 #define LmSEQ_FAILED_OPEN_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x009A)
2206 #define LmSEQ_XMIT_REQUEST_TYPE(LinkNum) (LmSCRATCH(LinkNum) + 0x009B)
2207 #define LmSEQ_M1_RESP_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x009C)
2208 #define LmSEQ_M1_LAST_LOADED_SGE(LinkNum) (LmSCRATCH(LinkNum) + 0x009D)
2209 #define LmSEQ_M1_SAVE_SCBPTR(LinkNum) (LmSCRATCH(LinkNum) + 0x009E)
2210 
2211 /* Mode dependent scratch page 0 macros for mode 2 (non-common) */
2212 #define LmSEQ_PORT_COUNTER(LinkNum) (LmSCRATCH(LinkNum) + 0x010E)
2213 #define LmSEQ_PM_TABLE_PTR(LinkNum) (LmSCRATCH(LinkNum) + 0x0110)
2214 #define LmSEQ_SATA_INTERLOCK_TMR_SAVE(LinkNum) (LmSCRATCH(LinkNum) + 0x0112)
2215 #define LmSEQ_IP_BITL(LinkNum) (LmSCRATCH(LinkNum) + 0x0114)
2216 #define LmSEQ_COPY_SMP_CONN_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x0116)
2217 #define LmSEQ_P0M2_OFFS1AH(LinkNum) (LmSCRATCH(LinkNum) + 0x011A)
2218 
2219 /* Mode dependent scratch page 0 macros for modes 4/5 (non-common) */
2220 /* Absolute offsets */
2221 #define LmSEQ_SAVED_OOB_STATUS(LinkNum) (LmSCRATCH(LinkNum) + 0x006E)
2222 #define LmSEQ_SAVED_OOB_MODE(LinkNum) (LmSCRATCH(LinkNum) + 0x006F)
2223 #define LmSEQ_Q_LINK_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x0070)
2224 #define LmSEQ_LINK_RST_ERR(LinkNum) (LmSCRATCH(LinkNum) + 0x0072)
2225 #define LmSEQ_SAVED_OOB_SIGNALS(LinkNum) (LmSCRATCH(LinkNum) + 0x0073)
2226 #define LmSEQ_SAS_RESET_MODE(LinkNum) (LmSCRATCH(LinkNum) + 0x0074)
2227 #define LmSEQ_LINK_RESET_RETRY_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0075)
2228 #define LmSEQ_NUM_LINK_RESET_RETRIES(LinkNum) (LmSCRATCH(LinkNum) + 0x0076)
2229 #define LmSEQ_OOB_INT_ENABLES(LinkNum) (LmSCRATCH(LinkNum) + 0x0078)
2230 #define LmSEQ_NOTIFY_TIMER_DOWN_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x007A)
2231 #define LmSEQ_NOTIFY_TIMER_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x007C)
2232 #define LmSEQ_NOTIFY_TIMER_INITIAL_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x007E)
2233 
2234 /* Mode dependent scratch page 1, mode 0 and mode 1 */
2235 #define LmSEQ_SG_LIST_PTR_ADDR0(LinkNum) (LmSCRATCH(LinkNum) + 0x0020)
2236 #define LmSEQ_SG_LIST_PTR_ADDR1(LinkNum) (LmSCRATCH(LinkNum) + 0x0030)
2237 #define LmSEQ_M1_SG_LIST_PTR_ADDR0(LinkNum) (LmSCRATCH(LinkNum) + 0x00A0)
2238 #define LmSEQ_M1_SG_LIST_PTR_ADDR1(LinkNum) (LmSCRATCH(LinkNum) + 0x00B0)
2239 
2240 /* Mode dependent scratch page 1 macros for mode 2 */
2241 /* Absolute offsets */
2242 #define LmSEQ_INVALID_DWORD_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0120)
2243 #define LmSEQ_DISPARITY_ERROR_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0124)
2244 #define LmSEQ_LOSS_OF_SYNC_COUNT(LinkNum) (LmSCRATCH(LinkNum) + 0x0128)
2245 
2246 /* Mode dependent scratch page 1 macros for mode 4/5 */
2247 #define LmSEQ_FRAME_TYPE_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00E0)
2248 #define LmSEQ_HASHED_DEST_ADDR_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00E1)
2249 #define LmSEQ_HASHED_SRC_ADDR_MASK_PRINT(LinkNum) (LmSCRATCH(LinkNum) + 0x00E4)
2250 #define LmSEQ_HASHED_SRC_ADDR_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00E5)
2251 #define LmSEQ_NUM_FILL_BYTES_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00EB)
2252 #define LmSEQ_TAG_MASK(LinkNum) (LmSCRATCH(LinkNum) + 0x00F0)
2253 #define LmSEQ_TARGET_PORT_XFER_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x00F2)
2254 #define LmSEQ_DATA_OFFSET(LinkNum) (LmSCRATCH(LinkNum) + 0x00F4)
2255 
2256 /* Mode dependent scratch page 2 macros for mode 0 */
2257 /* Absolute offsets */
2258 #define LmSEQ_SMP_RCV_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0040)
2259 #define LmSEQ_DEVICE_BITS(LinkNum) (LmSCRATCH(LinkNum) + 0x005B)
2260 #define LmSEQ_SDB_DDB(LinkNum) (LmSCRATCH(LinkNum) + 0x005C)
2261 #define LmSEQ_SDB_NUM_TAGS(LinkNum) (LmSCRATCH(LinkNum) + 0x005E)
2262 #define LmSEQ_SDB_CURR_TAG(LinkNum) (LmSCRATCH(LinkNum) + 0x005F)
2263 
2264 /* Mode dependent scratch page 2 macros for mode 1 */
2265 /* Absolute offsets */
2266 /* byte 0 bits 1-0 are domain select. */
2267 #define LmSEQ_TX_ID_ADDR_FRAME(LinkNum) (LmSCRATCH(LinkNum) + 0x00C0)
2268 #define LmSEQ_OPEN_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x00C8)
2269 #define LmSEQ_SRST_AS_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x00CC)
2270 #define LmSEQ_LAST_LOADED_SG_EL(LinkNum) (LmSCRATCH(LinkNum) + 0x00D4)
2271 
2272 /* Mode dependent scratch page 2 macros for mode 2 */
2273 /* Absolute offsets */
2274 #define LmSEQ_STP_SHUTDOWN_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0140)
2275 #define LmSEQ_CLOSE_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0144)
2276 #define LmSEQ_BREAK_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0148)
2277 #define LmSEQ_DWS_RESET_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x014C)
2278 #define LmSEQ_SATA_INTERLOCK_TIMER_TERM_TS(LinkNum) \
2279  (LmSCRATCH(LinkNum) + 0x0150)
2280 #define LmSEQ_MCTL_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0154)
2281 
2282 /* Mode dependent scratch page 2 macros for mode 5 */
2283 #define LmSEQ_COMINIT_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0160)
2284 #define LmSEQ_RCV_ID_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0164)
2285 #define LmSEQ_RCV_FIS_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x0168)
2286 #define LmSEQ_DEV_PRES_TIMER_TERM_TS(LinkNum) (LmSCRATCH(LinkNum) + 0x016C)
2287 
2288 /* Mode dependent scratch page 3 macros for modes 0 and 1 */
2289 /* None defined */
2290 
2291 /* Mode dependent scratch page 3 macros for modes 2 and 5 */
2292 /* None defined */
2293 
2294 /* Mode Independent Scratch page 0 macros. */
2295 #define LmSEQ_Q_TGTXFR_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x0180)
2296 #define LmSEQ_Q_TGTXFR_TAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x0182)
2297 #define LmSEQ_LINK_NUMBER(LinkNum) (LmSCRATCH(LinkNum) + 0x0186)
2298 #define LmSEQ_SCRATCH_FLAGS(LinkNum) (LmSCRATCH(LinkNum) + 0x0187)
2299 /*
2300  * Currently only bit 0, SAS_DWSAQD, is used.
2301  */
2302 #define SAS_DWSAQD 0x01 /*
2303  * DWSSTATUS: DWSAQD
2304  * bit las read in ISR.
2305  */
2306 #define LmSEQ_CONNECTION_STATE(LinkNum) (LmSCRATCH(LinkNum) + 0x0188)
2307 /* Connection states (byte 0) */
2308 #define SAS_WE_OPENED_CS 0x01
2309 #define SAS_DEVICE_OPENED_CS 0x02
2310 #define SAS_WE_SENT_DONE_CS 0x04
2311 #define SAS_DEVICE_SENT_DONE_CS 0x08
2312 #define SAS_WE_SENT_CLOSE_CS 0x10
2313 #define SAS_DEVICE_SENT_CLOSE_CS 0x20
2314 #define SAS_WE_SENT_BREAK_CS 0x40
2315 #define SAS_DEVICE_SENT_BREAK_CS 0x80
2316 /* Connection states (byte 1) */
2317 #define SAS_OPN_TIMEOUT_OR_OPN_RJCT_CS 0x01
2318 #define SAS_AIP_RECEIVED_CS 0x02
2319 #define SAS_CREDIT_TIMEOUT_OCCURRED_CS 0x04
2320 #define SAS_ACKNAK_TIMEOUT_OCCURRED_CS 0x08
2321 #define SAS_SMPRSP_TIMEOUT_OCCURRED_CS 0x10
2322 #define SAS_DONE_TIMEOUT_OCCURRED_CS 0x20
2323 /* Connection states (byte 2) */
2324 #define SAS_SMP_RESPONSE_RECEIVED_CS 0x01
2325 #define SAS_INTLK_TIMEOUT_OCCURRED_CS 0x02
2326 #define SAS_DEVICE_SENT_DMAT_CS 0x04
2327 #define SAS_DEVICE_SENT_SYNCSRST_CS 0x08
2328 #define SAS_CLEARING_AFFILIATION_CS 0x20
2329 #define SAS_RXTASK_ACTIVE_CS 0x40
2330 #define SAS_TXTASK_ACTIVE_CS 0x80
2331 /* Connection states (byte 3) */
2332 #define SAS_PHY_LOSS_OF_SIGNAL_CS 0x01
2333 #define SAS_DWS_TIMER_EXPIRED_CS 0x02
2334 #define SAS_LINK_RESET_NOT_COMPLETE_CS 0x04
2335 #define SAS_PHY_DISABLED_CS 0x08
2336 #define SAS_LINK_CTL_TASK_ACTIVE_CS 0x10
2337 #define SAS_PHY_EVENT_TASK_ACTIVE_CS 0x20
2338 #define SAS_DEVICE_SENT_ID_FRAME_CS 0x40
2339 #define SAS_DEVICE_SENT_REG_FIS_CS 0x40
2340 #define SAS_DEVICE_SENT_HARD_RESET_CS 0x80
2341 #define SAS_PHY_IS_DOWN_FLAGS (SAS_PHY_LOSS_OF_SIGNAL_CS|\
2342  SAS_DWS_TIMER_EXPIRED_CS |\
2343  SAS_LINK_RESET_NOT_COMPLETE_CS|\
2344  SAS_PHY_DISABLED_CS)
2345 
2346 #define SAS_LINK_CTL_PHY_EVENT_FLAGS (SAS_LINK_CTL_TASK_ACTIVE_CS |\
2347  SAS_PHY_EVENT_TASK_ACTIVE_CS |\
2348  SAS_DEVICE_SENT_ID_FRAME_CS |\
2349  SAS_DEVICE_SENT_HARD_RESET_CS)
2351 #define LmSEQ_CONCTL(LinkNum) (LmSCRATCH(LinkNum) + 0x018C)
2352 #define LmSEQ_CONSTAT(LinkNum) (LmSCRATCH(LinkNum) + 0x018E)
2353 #define LmSEQ_CONNECTION_MODES(LinkNum) (LmSCRATCH(LinkNum) + 0x018F)
2354 #define LmSEQ_REG1_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0192)
2355 #define LmSEQ_REG2_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0194)
2356 #define LmSEQ_REG3_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0196)
2357 #define LmSEQ_REG0_ISR(LinkNum) (LmSCRATCH(LinkNum) + 0x0198)
2359 /* Mode independent scratch page 1 macros. */
2360 #define LmSEQ_EST_NEXUS_SCBPTR0(LinkNum) (LmSCRATCH(LinkNum) + 0x01A0)
2361 #define LmSEQ_EST_NEXUS_SCBPTR1(LinkNum) (LmSCRATCH(LinkNum) + 0x01A2)
2362 #define LmSEQ_EST_NEXUS_SCBPTR2(LinkNum) (LmSCRATCH(LinkNum) + 0x01A4)
2363 #define LmSEQ_EST_NEXUS_SCBPTR3(LinkNum) (LmSCRATCH(LinkNum) + 0x01A6)
2364 #define LmSEQ_EST_NEXUS_SCB_OPCODE0(LinkNum) (LmSCRATCH(LinkNum) + 0x01A8)
2365 #define LmSEQ_EST_NEXUS_SCB_OPCODE1(LinkNum) (LmSCRATCH(LinkNum) + 0x01A9)
2366 #define LmSEQ_EST_NEXUS_SCB_OPCODE2(LinkNum) (LmSCRATCH(LinkNum) + 0x01AA)
2367 #define LmSEQ_EST_NEXUS_SCB_OPCODE3(LinkNum) (LmSCRATCH(LinkNum) + 0x01AB)
2368 #define LmSEQ_EST_NEXUS_SCB_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x01AC)
2369 #define LmSEQ_EST_NEXUS_SCB_TAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01AD)
2370 #define LmSEQ_EST_NEXUS_BUF_AVAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01AE)
2371 #define LmSEQ_TIMEOUT_CONST(LinkNum) (LmSCRATCH(LinkNum) + 0x01B8)
2372 #define LmSEQ_ISR_SAVE_SINDEX(LinkNum) (LmSCRATCH(LinkNum) + 0x01BC)
2373 #define LmSEQ_ISR_SAVE_DINDEX(LinkNum) (LmSCRATCH(LinkNum) + 0x01BE)
2375 /* Mode independent scratch page 2 macros. */
2376 #define LmSEQ_EMPTY_SCB_PTR0(LinkNum) (LmSCRATCH(LinkNum) + 0x01C0)
2377 #define LmSEQ_EMPTY_SCB_PTR1(LinkNum) (LmSCRATCH(LinkNum) + 0x01C2)
2378 #define LmSEQ_EMPTY_SCB_PTR2(LinkNum) (LmSCRATCH(LinkNum) + 0x01C4)
2379 #define LmSEQ_EMPTY_SCB_PTR3(LinkNum) (LmSCRATCH(LinkNum) + 0x01C6)
2380 #define LmSEQ_EMPTY_SCB_OPCD0(LinkNum) (LmSCRATCH(LinkNum) + 0x01C8)
2381 #define LmSEQ_EMPTY_SCB_OPCD1(LinkNum) (LmSCRATCH(LinkNum) + 0x01C9)
2382 #define LmSEQ_EMPTY_SCB_OPCD2(LinkNum) (LmSCRATCH(LinkNum) + 0x01CA)
2383 #define LmSEQ_EMPTY_SCB_OPCD3(LinkNum) (LmSCRATCH(LinkNum) + 0x01CB)
2384 #define LmSEQ_EMPTY_SCB_HEAD(LinkNum) (LmSCRATCH(LinkNum) + 0x01CC)
2385 #define LmSEQ_EMPTY_SCB_TAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01CD)
2386 #define LmSEQ_EMPTY_BUFS_AVAIL(LinkNum) (LmSCRATCH(LinkNum) + 0x01CE)
2387 #define LmSEQ_ATA_SCR_REGS(LinkNum) (LmSCRATCH(LinkNum) + 0x01D4)
2389 /* Mode independent scratch page 3 macros. */
2390 #define LmSEQ_DEV_PRES_TMR_TOUT_CONST(LinkNum) (LmSCRATCH(LinkNum) + 0x01E0)
2391 #define LmSEQ_SATA_INTERLOCK_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01E4)
2392 #define LmSEQ_STP_SHUTDOWN_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01E8)
2393 #define LmSEQ_SRST_ASSERT_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01EC)
2394 #define LmSEQ_RCV_FIS_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01F0)
2395 #define LmSEQ_ONE_MILLISEC_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01F4)
2396 #define LmSEQ_TEN_MS_COMINIT_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01F8)
2397 #define LmSEQ_SMP_RCV_TIMEOUT(LinkNum) (LmSCRATCH(LinkNum) + 0x01FC)
2398 
2399 #endif