21 #include <linux/kernel.h>
27 #include <mach/hardware.h>
28 #include <mach/cputype.h>
29 #include <mach/common.h>
32 #define FIQ_REG0_OFFSET 0x0000
33 #define FIQ_REG1_OFFSET 0x0004
34 #define IRQ_REG0_OFFSET 0x0008
35 #define IRQ_REG1_OFFSET 0x000C
36 #define IRQ_ENT_REG0_OFFSET 0x0018
37 #define IRQ_ENT_REG1_OFFSET 0x001C
38 #define IRQ_INCTL_REG_OFFSET 0x0020
39 #define IRQ_EABASE_REG_OFFSET 0x0024
40 #define IRQ_INTPRI0_REG_OFFSET 0x0030
41 #define IRQ_INTPRI7_REG_OFFSET 0x004C
43 static inline void davinci_irq_writel(
unsigned long value,
int offset)
49 davinci_alloc_gc(
void __iomem *base,
unsigned int irq_start,
unsigned int num)
51 struct irq_chip_generic *
gc;
52 struct irq_chip_type *
ct;
56 pr_err(
"%s: irq_alloc_generic_chip for IRQ %u failed\n",
108 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
109 pri |= (*davinci_def_priorities & 0x07) <<
j;
110 davinci_irq_writel(pri, i);