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hardware.h
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1 /*
2  * arch/arm/mach-pxa/include/mach/hardware.h
3  *
4  * Author: Nicolas Pitre
5  * Created: Jun 15, 2001
6  * Copyright: MontaVista Software Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #ifndef __ASM_ARCH_HARDWARE_H
14 #define __ASM_ARCH_HARDWARE_H
15 
16 #include <mach/addr-map.h>
17 
18 /*
19  * Workarounds for at least 2 errata so far require this.
20  * The mapping is set in mach-pxa/generic.c.
21  */
22 #define UNCACHED_PHYS_0 0xff000000
23 #define UNCACHED_ADDR UNCACHED_PHYS_0
24 
25 /*
26  * Intel PXA2xx internal register mapping:
27  *
28  * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
29  * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
30  * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
31  * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
32  * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
33  * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
34  * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
35  *
36  * Note that not all PXA2xx chips implement all those addresses, and the
37  * kernel only maps the minimum needed range of this mapping.
38  */
39 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
40 #define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
41 
42 #ifndef __ASSEMBLY__
43 # define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
44 
45 /* With indexed regs we don't want to feed the index through io_p2v()
46  especially if it is a variable, otherwise horrible code will result. */
47 # define __REG2(x,y) \
48  (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
49 
50 # define __PREG(x) (io_v2p((u32)&(x)))
51 
52 #else
53 
54 # define __REG(x) io_p2v(x)
55 # define __PREG(x) io_v2p(x)
56 
57 #endif
58 
59 #ifndef __ASSEMBLY__
60 
61 #include <asm/cputype.h>
62 
63 /*
64  * CPU Stepping CPU_ID JTAG_ID
65  *
66  * PXA210 B0 0x69052922 0x2926C013
67  * PXA210 B1 0x69052923 0x3926C013
68  * PXA210 B2 0x69052924 0x4926C013
69  * PXA210 C0 0x69052D25 0x5926C013
70  *
71  * PXA250 A0 0x69052100 0x09264013
72  * PXA250 A1 0x69052101 0x19264013
73  * PXA250 B0 0x69052902 0x29264013
74  * PXA250 B1 0x69052903 0x39264013
75  * PXA250 B2 0x69052904 0x49264013
76  * PXA250 C0 0x69052D05 0x59264013
77  *
78  * PXA255 A0 0x69052D06 0x69264013
79  *
80  * PXA26x A0 0x69052903 0x39264013
81  * PXA26x B0 0x69052D05 0x59264013
82  *
83  * PXA27x A0 0x69054110 0x09265013
84  * PXA27x A1 0x69054111 0x19265013
85  * PXA27x B0 0x69054112 0x29265013
86  * PXA27x B1 0x69054113 0x39265013
87  * PXA27x C0 0x69054114 0x49265013
88  * PXA27x C5 0x69054117 0x79265013
89  *
90  * PXA30x A0 0x69056880 0x0E648013
91  * PXA30x A1 0x69056881 0x1E648013
92  * PXA31x A0 0x69056890 0x0E649013
93  * PXA31x A1 0x69056891 0x1E649013
94  * PXA31x A2 0x69056892 0x2E649013
95  * PXA32x B1 0x69056825 0x5E642013
96  * PXA32x B2 0x69056826 0x6E642013
97  *
98  * PXA930 B0 0x69056835 0x5E643013
99  * PXA930 B1 0x69056837 0x7E643013
100  * PXA930 B2 0x69056838 0x8E643013
101  *
102  * PXA935 A0 0x56056931 0x1E653013
103  * PXA935 B0 0x56056936 0x6E653013
104  * PXA935 B1 0x56056938 0x8E653013
105  */
106 #ifdef CONFIG_PXA25x
107 #define __cpu_is_pxa210(id) \
108  ({ \
109  unsigned int _id = (id) & 0xf3f0; \
110  _id == 0x2120; \
111  })
112 
113 #define __cpu_is_pxa250(id) \
114  ({ \
115  unsigned int _id = (id) & 0xf3ff; \
116  _id <= 0x2105; \
117  })
118 
119 #define __cpu_is_pxa255(id) \
120  ({ \
121  unsigned int _id = (id) & 0xffff; \
122  _id == 0x2d06; \
123  })
124 
125 #define __cpu_is_pxa25x(id) \
126  ({ \
127  unsigned int _id = (id) & 0xf300; \
128  _id == 0x2100; \
129  })
130 #else
131 #define __cpu_is_pxa210(id) (0)
132 #define __cpu_is_pxa250(id) (0)
133 #define __cpu_is_pxa255(id) (0)
134 #define __cpu_is_pxa25x(id) (0)
135 #endif
136 
137 #ifdef CONFIG_PXA27x
138 #define __cpu_is_pxa27x(id) \
139  ({ \
140  unsigned int _id = (id) >> 4 & 0xfff; \
141  _id == 0x411; \
142  })
143 #else
144 #define __cpu_is_pxa27x(id) (0)
145 #endif
146 
147 #ifdef CONFIG_CPU_PXA300
148 #define __cpu_is_pxa300(id) \
149  ({ \
150  unsigned int _id = (id) >> 4 & 0xfff; \
151  _id == 0x688; \
152  })
153 #else
154 #define __cpu_is_pxa300(id) (0)
155 #endif
156 
157 #ifdef CONFIG_CPU_PXA310
158 #define __cpu_is_pxa310(id) \
159  ({ \
160  unsigned int _id = (id) >> 4 & 0xfff; \
161  _id == 0x689; \
162  })
163 #else
164 #define __cpu_is_pxa310(id) (0)
165 #endif
166 
167 #ifdef CONFIG_CPU_PXA320
168 #define __cpu_is_pxa320(id) \
169  ({ \
170  unsigned int _id = (id) >> 4 & 0xfff; \
171  _id == 0x603 || _id == 0x682; \
172  })
173 #else
174 #define __cpu_is_pxa320(id) (0)
175 #endif
176 
177 #ifdef CONFIG_CPU_PXA930
178 #define __cpu_is_pxa930(id) \
179  ({ \
180  unsigned int _id = (id) >> 4 & 0xfff; \
181  _id == 0x683; \
182  })
183 #else
184 #define __cpu_is_pxa930(id) (0)
185 #endif
186 
187 #ifdef CONFIG_CPU_PXA935
188 #define __cpu_is_pxa935(id) \
189  ({ \
190  unsigned int _id = (id) >> 4 & 0xfff; \
191  _id == 0x693; \
192  })
193 #else
194 #define __cpu_is_pxa935(id) (0)
195 #endif
196 
197 #ifdef CONFIG_CPU_PXA955
198 #define __cpu_is_pxa955(id) \
199  ({ \
200  unsigned int _id = (id) >> 4 & 0xfff; \
201  _id == 0x581 || _id == 0xc08 \
202  || _id == 0xb76; \
203  })
204 #else
205 #define __cpu_is_pxa955(id) (0)
206 #endif
207 
208 #define cpu_is_pxa210() \
209  ({ \
210  __cpu_is_pxa210(read_cpuid_id()); \
211  })
212 
213 #define cpu_is_pxa250() \
214  ({ \
215  __cpu_is_pxa250(read_cpuid_id()); \
216  })
217 
218 #define cpu_is_pxa255() \
219  ({ \
220  __cpu_is_pxa255(read_cpuid_id()); \
221  })
222 
223 #define cpu_is_pxa25x() \
224  ({ \
225  __cpu_is_pxa25x(read_cpuid_id()); \
226  })
227 
228 #define cpu_is_pxa27x() \
229  ({ \
230  __cpu_is_pxa27x(read_cpuid_id()); \
231  })
232 
233 #define cpu_is_pxa300() \
234  ({ \
235  __cpu_is_pxa300(read_cpuid_id()); \
236  })
237 
238 #define cpu_is_pxa310() \
239  ({ \
240  __cpu_is_pxa310(read_cpuid_id()); \
241  })
242 
243 #define cpu_is_pxa320() \
244  ({ \
245  __cpu_is_pxa320(read_cpuid_id()); \
246  })
247 
248 #define cpu_is_pxa930() \
249  ({ \
250  __cpu_is_pxa930(read_cpuid_id()); \
251  })
252 
253 #define cpu_is_pxa935() \
254  ({ \
255  __cpu_is_pxa935(read_cpuid_id()); \
256  })
257 
258 #define cpu_is_pxa955() \
259  ({ \
260  __cpu_is_pxa955(read_cpuid_id()); \
261  })
262 
263 
264 /*
265  * CPUID Core Generation Bit
266  * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
267  */
268 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
269 #define __cpu_is_pxa2xx(id) \
270  ({ \
271  unsigned int _id = (id) >> 13 & 0x7; \
272  _id <= 0x2; \
273  })
274 #else
275 #define __cpu_is_pxa2xx(id) (0)
276 #endif
277 
278 #ifdef CONFIG_PXA3xx
279 #define __cpu_is_pxa3xx(id) \
280  ({ \
281  __cpu_is_pxa300(id) \
282  || __cpu_is_pxa310(id) \
283  || __cpu_is_pxa320(id) \
284  || __cpu_is_pxa93x(id); \
285  })
286 #else
287 #define __cpu_is_pxa3xx(id) (0)
288 #endif
289 
290 #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
291 #define __cpu_is_pxa93x(id) \
292  ({ \
293  __cpu_is_pxa930(id) \
294  || __cpu_is_pxa935(id); \
295  })
296 #else
297 #define __cpu_is_pxa93x(id) (0)
298 #endif
299 
300 #ifdef CONFIG_PXA95x
301 #define __cpu_is_pxa95x(id) \
302  ({ \
303  __cpu_is_pxa955(id); \
304  })
305 #else
306 #define __cpu_is_pxa95x(id) (0)
307 #endif
308 
309 #define cpu_is_pxa2xx() \
310  ({ \
311  __cpu_is_pxa2xx(read_cpuid_id()); \
312  })
313 
314 #define cpu_is_pxa3xx() \
315  ({ \
316  __cpu_is_pxa3xx(read_cpuid_id()); \
317  })
318 
319 #define cpu_is_pxa93x() \
320  ({ \
321  __cpu_is_pxa93x(read_cpuid_id()); \
322  })
323 
324 #define cpu_is_pxa95x() \
325  ({ \
326  __cpu_is_pxa95x(read_cpuid_id()); \
327  })
328 
329 /*
330  * return current memory and LCD clock frequency in units of 10kHz
331  */
332 extern unsigned int get_memclk_frequency_10khz(void);
333 
334 /* return the clock tick rate of the OS timer */
335 extern unsigned long get_clock_tick_rate(void);
336 #endif
337 
338 #endif /* _ASM_ARCH_HARDWARE_H */
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