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dma.h
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1 /* linux/arch/arm/mach-s3c6400/include/mach/dma.h
2  *
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  * Ben Dooks <[email protected]>
6  * http://armlinux.simtec.co.uk/
7  *
8  * S3C6400 - DMA support
9  */
10 
11 #ifndef __ASM_ARCH_DMA_H
12 #define __ASM_ARCH_DMA_H __FILE__
13 
14 #define S3C_DMA_CHANNELS (16)
15 
16 /* see mach-s3c2410/dma.h for notes on dma channel numbers */
17 
18 /* Note, for the S3C64XX architecture we keep the DMACH_
19  * defines in the order they are allocated to [S]DMA0/[S]DMA1
20  * so that is easy to do DHACH_ -> DMA controller conversion
21  */
22 enum dma_ch {
23  /* DMA0/SDMA0 */
24  DMACH_DT_PROP = -1, /* not yet supported, do not use */
25  DMACH_UART0 = 0,
26  DMACH_UART0_SRC2,
27  DMACH_UART1,
28  DMACH_UART1_SRC2,
29  DMACH_UART2,
30  DMACH_UART2_SRC2,
31  DMACH_UART3,
32  DMACH_UART3_SRC2,
33  DMACH_PCM0_TX,
34  DMACH_PCM0_RX,
35  DMACH_I2S0_OUT,
36  DMACH_I2S0_IN,
37  DMACH_SPI0_TX,
38  DMACH_SPI0_RX,
39  DMACH_HSI_I2SV40_TX,
40  DMACH_HSI_I2SV40_RX,
41 
42  /* DMA1/SDMA1 */
43  DMACH_PCM1_TX = 16,
44  DMACH_PCM1_RX,
45  DMACH_I2S1_OUT,
46  DMACH_I2S1_IN,
47  DMACH_SPI1_TX,
48  DMACH_SPI1_RX,
49  DMACH_AC97_PCMOUT,
50  DMACH_AC97_PCMIN,
51  DMACH_AC97_MICIN,
52  DMACH_PWM,
53  DMACH_IRDA,
54  DMACH_EXTERNAL,
55  DMACH_RES1,
56  DMACH_RES2,
57  DMACH_SECURITY_RX, /* SDMA1 only */
58  DMACH_SECURITY_TX, /* SDMA1 only */
59  DMACH_MAX /* the end */
60 };
61 
62 static inline bool samsung_dma_has_circular(void)
63 {
64  return true;
65 }
66 
67 static inline bool samsung_dma_is_dmadev(void)
68 {
69  return false;
70 }
71 #define S3C2410_DMAF_CIRCULAR (1 << 0)
72 
73 #include <plat/dma.h>
74 
75 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
76 
77 struct s3c64xx_dma_buff;
78 
85 struct s3c64xx_dma_buff {
86  struct s3c64xx_dma_buff *next;
87 
88  void *pw;
89  struct pl080s_lli *lli;
90  dma_addr_t lli_dma;
91 };
92 
93 struct s3c64xx_dmac;
94 
95 struct s3c2410_dma_chan {
96  unsigned char number; /* number of this dma channel */
97  unsigned char in_use; /* channel allocated */
98  unsigned char bit; /* bit for enable/disable/etc */
99  unsigned char hw_width;
100  unsigned char peripheral;
101 
102  unsigned int flags;
103  enum dma_data_direction source;
104 
105 
106  dma_addr_t dev_addr;
107 
108  struct s3c2410_dma_client *client;
109  struct s3c64xx_dmac *dmac; /* pointer to controller */
110 
111  void __iomem *regs;
112 
113  /* cdriver callbacks */
114  s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
115  s3c2410_dma_opfn_t op_fn; /* channel op callback */
116 
117  /* buffer list and information */
118  struct s3c64xx_dma_buff *curr; /* current dma buffer */
119  struct s3c64xx_dma_buff *next; /* next buffer to load */
120  struct s3c64xx_dma_buff *end; /* end of queue */
121 
122  /* note, when channel is running in circular mode, curr is the
123  * first buffer enqueued, end is the last and curr is where the
124  * last buffer-done event is set-at. The buffers are not freed
125  * and the last buffer hardware descriptor points back to the
126  * first.
127  */
128 };
129 
130 #include <plat/dma-core.h>
131 
132 #endif /* __ASM_ARCH_IRQ_H */
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