Go to the documentation of this file. 1 #ifndef __bif_slave_defs_h
2 #define __bif_slave_defs_h
18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
71 #define reg_page_size 8192
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
89 unsigned int slave_id : 3;
90 unsigned int use_slave_id : 1;
91 unsigned int boot_rdy : 1;
94 unsigned int dummy1 : 25;
96 #define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
97 #define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
101 unsigned int ch0_mode : 1;
102 unsigned int ch1_mode : 1;
103 unsigned int ch2_mode : 1;
104 unsigned int ch3_mode : 1;
105 unsigned int dummy1 : 28;
107 #define REG_RD_ADDR_bif_slave_r_slave_mode 4
111 unsigned int rd_hold : 2;
113 unsigned int access_ctrl : 1;
114 unsigned int data_cs : 2;
115 unsigned int dummy1 : 26;
117 #define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
118 #define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
122 unsigned int rd_hold : 2;
124 unsigned int access_ctrl : 1;
125 unsigned int data_cs : 2;
126 unsigned int dummy1 : 26;
128 #define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
129 #define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
133 unsigned int rd_hold : 2;
135 unsigned int access_ctrl : 1;
136 unsigned int data_cs : 2;
137 unsigned int dummy1 : 26;
139 #define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
140 #define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
144 unsigned int rd_hold : 2;
146 unsigned int access_ctrl : 1;
147 unsigned int data_cs : 2;
148 unsigned int dummy1 : 26;
150 #define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
151 #define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
155 unsigned int brin_mode : 1;
156 unsigned int brout_mode : 3;
157 unsigned int bg_mode : 3;
159 unsigned int acquire : 1;
160 unsigned int settle_time : 2;
161 unsigned int dram_ctrl : 1;
162 unsigned int dummy1 : 19;
164 #define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
165 #define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
169 unsigned int init_mode : 1;
171 unsigned int brin : 1;
172 unsigned int brout : 1;
174 unsigned int dummy1 : 27;
176 #define REG_RD_ADDR_bif_slave_r_arb_stat 36
180 unsigned int bus_release : 1;
181 unsigned int bus_acquire : 1;
182 unsigned int dummy1 : 30;
184 #define REG_RD_ADDR_bif_slave_rw_intr_mask 64
185 #define REG_WR_ADDR_bif_slave_rw_intr_mask 64
189 unsigned int bus_release : 1;
190 unsigned int bus_acquire : 1;
191 unsigned int dummy1 : 30;
193 #define REG_RD_ADDR_bif_slave_rw_ack_intr 68
194 #define REG_WR_ADDR_bif_slave_rw_ack_intr 68
198 unsigned int bus_release : 1;
199 unsigned int bus_acquire : 1;
200 unsigned int dummy1 : 30;
202 #define REG_RD_ADDR_bif_slave_r_intr 72
206 unsigned int bus_release : 1;
207 unsigned int bus_acquire : 1;
208 unsigned int dummy1 : 30;
210 #define REG_RD_ADDR_bif_slave_r_masked_intr 76