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ptrace.h
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1 /*
2  * Copyright (C) 2001 PPC64 Team, IBM Corp
3  *
4  * This struct defines the way the registers are stored on the
5  * kernel stack during a system call or other kernel entry.
6  *
7  * this should only contain volatile regs
8  * since we can keep non-volatile in the thread_struct
9  * should set this up when only volatiles are saved
10  * by intr code.
11  *
12  * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
13  * that the overall structure is a multiple of 16 bytes in length.
14  *
15  * Note that the offsets of the fields in this struct correspond with
16  * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
17  *
18  * This program is free software; you can redistribute it and/or
19  * modify it under the terms of the GNU General Public License
20  * as published by the Free Software Foundation; either version
21  * 2 of the License, or (at your option) any later version.
22  */
23 #ifndef _UAPI_ASM_POWERPC_PTRACE_H
24 #define _UAPI_ASM_POWERPC_PTRACE_H
25 
26 
27 #include <linux/types.h>
28 
29 #ifndef __ASSEMBLY__
30 
31 struct pt_regs {
32  unsigned long gpr[32];
33  unsigned long nip;
34  unsigned long msr;
35  unsigned long orig_gpr3; /* Used for restarting system calls */
36  unsigned long ctr;
37  unsigned long link;
38  unsigned long xer;
39  unsigned long ccr;
40 #ifdef __powerpc64__
41  unsigned long softe; /* Soft enabled/disabled */
42 #else
43  unsigned long mq; /* 601 only (not used at present) */
44  /* Used on APUS to hold IPL value. */
45 #endif
46  unsigned long trap; /* Reason for being here */
47  /* N.B. for critical exceptions on 4xx, the dar and dsisr
48  fields are overloaded to hold srr0 and srr1. */
49  unsigned long dar; /* Fault registers */
50  unsigned long dsisr; /* on 4xx/Book-E used for ESR */
51  unsigned long result; /* Result of a system call */
52 };
53 
54 #endif /* __ASSEMBLY__ */
55 
56 
57 /*
58  * Offsets used by 'ptrace' system call interface.
59  * These can't be changed without breaking binary compatibility
60  * with MkLinux, etc.
61  */
62 #define PT_R0 0
63 #define PT_R1 1
64 #define PT_R2 2
65 #define PT_R3 3
66 #define PT_R4 4
67 #define PT_R5 5
68 #define PT_R6 6
69 #define PT_R7 7
70 #define PT_R8 8
71 #define PT_R9 9
72 #define PT_R10 10
73 #define PT_R11 11
74 #define PT_R12 12
75 #define PT_R13 13
76 #define PT_R14 14
77 #define PT_R15 15
78 #define PT_R16 16
79 #define PT_R17 17
80 #define PT_R18 18
81 #define PT_R19 19
82 #define PT_R20 20
83 #define PT_R21 21
84 #define PT_R22 22
85 #define PT_R23 23
86 #define PT_R24 24
87 #define PT_R25 25
88 #define PT_R26 26
89 #define PT_R27 27
90 #define PT_R28 28
91 #define PT_R29 29
92 #define PT_R30 30
93 #define PT_R31 31
94 
95 #define PT_NIP 32
96 #define PT_MSR 33
97 #define PT_ORIG_R3 34
98 #define PT_CTR 35
99 #define PT_LNK 36
100 #define PT_XER 37
101 #define PT_CCR 38
102 #ifndef __powerpc64__
103 #define PT_MQ 39
104 #else
105 #define PT_SOFTE 39
106 #endif
107 #define PT_TRAP 40
108 #define PT_DAR 41
109 #define PT_DSISR 42
110 #define PT_RESULT 43
111 #define PT_REGS_COUNT 44
112 
113 #define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
114 
115 #ifndef __powerpc64__
116 
117 #define PT_FPR31 (PT_FPR0 + 2*31)
118 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
119 
120 #else /* __powerpc64__ */
121 
122 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
123 
124 
125 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
126 #define PT_VSCR (PT_VR0 + 32*2 + 1)
127 #define PT_VRSAVE (PT_VR0 + 33*2)
128 
129 
130 /*
131  * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
132  */
133 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
134 #define PT_VSR31 (PT_VSR0 + 2*31)
135 #endif /* __powerpc64__ */
136 
137 /*
138  * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
139  * The transfer totals 34 quadword. Quadwords 0-31 contain the
140  * corresponding vector registers. Quadword 32 contains the vscr as the
141  * last word (offset 12) within that quadword. Quadword 33 contains the
142  * vrsave as the first word (offset 0) within the quadword.
143  *
144  * This definition of the VMX state is compatible with the current PPC32
145  * ptrace interface. This allows signal handling and ptrace to use the same
146  * structures. This also simplifies the implementation of a bi-arch
147  * (combined (32- and 64-bit) gdb.
148  */
149 #define PTRACE_GETVRREGS 18
150 #define PTRACE_SETVRREGS 19
151 
152 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and
153  * spefscr, in one go */
154 #define PTRACE_GETEVRREGS 20
155 #define PTRACE_SETEVRREGS 21
156 
157 /* Get the first 32 128bit VSX registers */
158 #define PTRACE_GETVSRREGS 27
159 #define PTRACE_SETVSRREGS 28
160 
161 /*
162  * Get or set a debug register. The first 16 are DABR registers and the
163  * second 16 are IABR registers.
164  */
165 #define PTRACE_GET_DEBUGREG 25
166 #define PTRACE_SET_DEBUGREG 26
167 
168 /* (new) PTRACE requests using the same numbers as x86 and the same
169  * argument ordering. Additionally, they support more registers too
170  */
171 #define PTRACE_GETREGS 12
172 #define PTRACE_SETREGS 13
173 #define PTRACE_GETFPREGS 14
174 #define PTRACE_SETFPREGS 15
175 #define PTRACE_GETREGS64 22
176 #define PTRACE_SETREGS64 23
177 
178 /* Calls to trace a 64bit program from a 32bit program */
179 #define PPC_PTRACE_PEEKTEXT_3264 0x95
180 #define PPC_PTRACE_PEEKDATA_3264 0x94
181 #define PPC_PTRACE_POKETEXT_3264 0x93
182 #define PPC_PTRACE_POKEDATA_3264 0x92
183 #define PPC_PTRACE_PEEKUSR_3264 0x91
184 #define PPC_PTRACE_POKEUSR_3264 0x90
185 
186 #define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
187 
188 #define PPC_PTRACE_GETHWDBGINFO 0x89
189 #define PPC_PTRACE_SETHWDEBUG 0x88
190 #define PPC_PTRACE_DELHWDEBUG 0x87
191 
192 #ifndef __ASSEMBLY__
193 
195  __u32 version; /* Only version 1 exists to date */
200  __u32 sizeof_condition; /* size of the DVC register */
202 };
203 
204 #endif /* __ASSEMBLY__ */
205 
206 /*
207  * features will have bits indication whether there is support for:
208  */
209 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
210 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
211 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
212 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
213 
214 #ifndef __ASSEMBLY__
215 
217  __u32 version; /* currently, version must be 1 */
218  __u32 trigger_type; /* only some combinations allowed */
219  __u32 addr_mode; /* address match mode */
220  __u32 condition_mode; /* break/watchpoint condition flags */
221  __u64 addr; /* break/watchpoint address */
222  __u64 addr2; /* range end or mask */
223  __u64 condition_value; /* contents of the DVC register */
224 };
225 
226 #endif /* __ASSEMBLY__ */
227 
228 /*
229  * Trigger Type
230  */
231 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
232 #define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
233 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
234 #define PPC_BREAKPOINT_TRIGGER_RW \
235  (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
236 
237 /*
238  * Address Mode
239  */
240 #define PPC_BREAKPOINT_MODE_EXACT 0x00000000
241 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
242 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
243 #define PPC_BREAKPOINT_MODE_MASK 0x00000003
244 
245 /*
246  * Condition Mode
247  */
248 #define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
249 #define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
250 #define PPC_BREAKPOINT_CONDITION_AND 0x00000001
251 #define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
252 #define PPC_BREAKPOINT_CONDITION_OR 0x00000002
253 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
254 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
255 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
256 #define PPC_BREAKPOINT_CONDITION_BE(n) \
257  (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
258 
259 #endif /* _UAPI_ASM_POWERPC_PTRACE_H */