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setup.c
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1 /*
2  * arch/sh/boards/superh/microdev/setup.c
3  *
4  * Copyright (C) 2003 Sean McGoogan ([email protected])
5  * Copyright (C) 2003, 2004 SuperH, Inc.
6  * Copyright (C) 2004, 2005 Paul Mundt
7  *
8  * SuperH SH4-202 MicroDev board support.
9  *
10  * May be copied or modified under the terms of the GNU General Public
11  * License. See linux/COPYING for more information.
12  */
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/ioport.h>
16 #include <video/s1d13xxxfb.h>
17 #include <mach/microdev.h>
18 #include <asm/io.h>
19 #include <asm/machvec.h>
20 #include <asm/sizes.h>
21 
22 static struct resource smc91x_resources[] = {
23  [0] = {
24  .start = 0x300,
25  .end = 0x300 + SZ_4K - 1,
26  .flags = IORESOURCE_MEM,
27  },
28  [1] = {
29  .start = MICRODEV_LINUX_IRQ_ETHERNET,
30  .end = MICRODEV_LINUX_IRQ_ETHERNET,
31  .flags = IORESOURCE_IRQ,
32  },
33 };
34 
35 static struct platform_device smc91x_device = {
36  .name = "smc91x",
37  .id = -1,
38  .num_resources = ARRAY_SIZE(smc91x_resources),
39  .resource = smc91x_resources,
40 };
41 
42 static struct s1d13xxxfb_regval s1d13806_initregs[] = {
43  { S1DREG_MISC, 0x00 },
44  { S1DREG_COM_DISP_MODE, 0x00 },
45  { S1DREG_GPIO_CNF0, 0x00 },
46  { S1DREG_GPIO_CNF1, 0x00 },
47  { S1DREG_GPIO_CTL0, 0x00 },
48  { S1DREG_GPIO_CTL1, 0x00 },
49  { S1DREG_CLK_CNF, 0x02 },
50  { S1DREG_LCD_CLK_CNF, 0x01 },
51  { S1DREG_CRT_CLK_CNF, 0x03 },
52  { S1DREG_MPLUG_CLK_CNF, 0x03 },
53  { S1DREG_CPU2MEM_WST_SEL, 0x02 },
54  { S1DREG_SDRAM_REF_RATE, 0x03 },
55  { S1DREG_SDRAM_TC0, 0x00 },
56  { S1DREG_SDRAM_TC1, 0x01 },
57  { S1DREG_MEM_CNF, 0x80 },
58  { S1DREG_PANEL_TYPE, 0x25 },
59  { S1DREG_MOD_RATE, 0x00 },
60  { S1DREG_LCD_DISP_HWIDTH, 0x63 },
61  { S1DREG_LCD_NDISP_HPER, 0x1e },
62  { S1DREG_TFT_FPLINE_START, 0x06 },
63  { S1DREG_TFT_FPLINE_PWIDTH, 0x03 },
64  { S1DREG_LCD_DISP_VHEIGHT0, 0x57 },
65  { S1DREG_LCD_DISP_VHEIGHT1, 0x02 },
66  { S1DREG_LCD_NDISP_VPER, 0x00 },
67  { S1DREG_TFT_FPFRAME_START, 0x0a },
68  { S1DREG_TFT_FPFRAME_PWIDTH, 0x81 },
69  { S1DREG_LCD_DISP_MODE, 0x03 },
70  { S1DREG_LCD_MISC, 0x00 },
71  { S1DREG_LCD_DISP_START0, 0x00 },
72  { S1DREG_LCD_DISP_START1, 0x00 },
73  { S1DREG_LCD_DISP_START2, 0x00 },
74  { S1DREG_LCD_MEM_OFF0, 0x90 },
75  { S1DREG_LCD_MEM_OFF1, 0x01 },
76  { S1DREG_LCD_PIX_PAN, 0x00 },
77  { S1DREG_LCD_DISP_FIFO_HTC, 0x00 },
78  { S1DREG_LCD_DISP_FIFO_LTC, 0x00 },
79  { S1DREG_CRT_DISP_HWIDTH, 0x63 },
80  { S1DREG_CRT_NDISP_HPER, 0x1f },
81  { S1DREG_CRT_HRTC_START, 0x04 },
82  { S1DREG_CRT_HRTC_PWIDTH, 0x8f },
83  { S1DREG_CRT_DISP_VHEIGHT0, 0x57 },
84  { S1DREG_CRT_DISP_VHEIGHT1, 0x02 },
85  { S1DREG_CRT_NDISP_VPER, 0x1b },
86  { S1DREG_CRT_VRTC_START, 0x00 },
87  { S1DREG_CRT_VRTC_PWIDTH, 0x83 },
88  { S1DREG_TV_OUT_CTL, 0x10 },
89  { S1DREG_CRT_DISP_MODE, 0x05 },
90  { S1DREG_CRT_DISP_START0, 0x00 },
91  { S1DREG_CRT_DISP_START1, 0x00 },
92  { S1DREG_CRT_DISP_START2, 0x00 },
93  { S1DREG_CRT_MEM_OFF0, 0x20 },
94  { S1DREG_CRT_MEM_OFF1, 0x03 },
95  { S1DREG_CRT_PIX_PAN, 0x00 },
96  { S1DREG_CRT_DISP_FIFO_HTC, 0x00 },
97  { S1DREG_CRT_DISP_FIFO_LTC, 0x00 },
98  { S1DREG_LCD_CUR_CTL, 0x00 },
99  { S1DREG_LCD_CUR_START, 0x01 },
100  { S1DREG_LCD_CUR_XPOS0, 0x00 },
101  { S1DREG_LCD_CUR_XPOS1, 0x00 },
102  { S1DREG_LCD_CUR_YPOS0, 0x00 },
103  { S1DREG_LCD_CUR_YPOS1, 0x00 },
104  { S1DREG_LCD_CUR_BCTL0, 0x00 },
105  { S1DREG_LCD_CUR_GCTL0, 0x00 },
106  { S1DREG_LCD_CUR_RCTL0, 0x00 },
107  { S1DREG_LCD_CUR_BCTL1, 0x1f },
108  { S1DREG_LCD_CUR_GCTL1, 0x3f },
109  { S1DREG_LCD_CUR_RCTL1, 0x1f },
110  { S1DREG_LCD_CUR_FIFO_HTC, 0x00 },
111  { S1DREG_CRT_CUR_CTL, 0x00 },
112  { S1DREG_CRT_CUR_START, 0x01 },
113  { S1DREG_CRT_CUR_XPOS0, 0x00 },
114  { S1DREG_CRT_CUR_XPOS1, 0x00 },
115  { S1DREG_CRT_CUR_YPOS0, 0x00 },
116  { S1DREG_CRT_CUR_YPOS1, 0x00 },
117  { S1DREG_CRT_CUR_BCTL0, 0x00 },
118  { S1DREG_CRT_CUR_GCTL0, 0x00 },
119  { S1DREG_CRT_CUR_RCTL0, 0x00 },
120  { S1DREG_CRT_CUR_BCTL1, 0x1f },
121  { S1DREG_CRT_CUR_GCTL1, 0x3f },
122  { S1DREG_CRT_CUR_RCTL1, 0x1f },
123  { S1DREG_CRT_CUR_FIFO_HTC, 0x00 },
124  { S1DREG_BBLT_CTL0, 0x00 },
125  { S1DREG_BBLT_CTL1, 0x00 },
126  { S1DREG_BBLT_CC_EXP, 0x00 },
127  { S1DREG_BBLT_OP, 0x00 },
128  { S1DREG_BBLT_SRC_START0, 0x00 },
129  { S1DREG_BBLT_SRC_START1, 0x00 },
130  { S1DREG_BBLT_SRC_START2, 0x00 },
131  { S1DREG_BBLT_DST_START0, 0x00 },
132  { S1DREG_BBLT_DST_START1, 0x00 },
133  { S1DREG_BBLT_DST_START2, 0x00 },
134  { S1DREG_BBLT_MEM_OFF0, 0x00 },
135  { S1DREG_BBLT_MEM_OFF1, 0x00 },
136  { S1DREG_BBLT_WIDTH0, 0x00 },
137  { S1DREG_BBLT_WIDTH1, 0x00 },
138  { S1DREG_BBLT_HEIGHT0, 0x00 },
139  { S1DREG_BBLT_HEIGHT1, 0x00 },
140  { S1DREG_BBLT_BGC0, 0x00 },
141  { S1DREG_BBLT_BGC1, 0x00 },
142  { S1DREG_BBLT_FGC0, 0x00 },
143  { S1DREG_BBLT_FGC1, 0x00 },
144  { S1DREG_LKUP_MODE, 0x00 },
145  { S1DREG_LKUP_ADDR, 0x00 },
146  { S1DREG_PS_CNF, 0x10 },
147  { S1DREG_PS_STATUS, 0x00 },
148  { S1DREG_CPU2MEM_WDOGT, 0x00 },
149  { S1DREG_COM_DISP_MODE, 0x02 },
150 };
151 
152 static struct s1d13xxxfb_pdata s1d13806_platform_data = {
153  .initregs = s1d13806_initregs,
154  .initregssize = ARRAY_SIZE(s1d13806_initregs),
155 };
156 
157 static struct resource s1d13806_resources[] = {
158  [0] = {
159  .start = 0x07200000,
160  .end = 0x07200000 + SZ_2M - 1,
161  .flags = IORESOURCE_MEM,
162  },
163  [1] = {
164  .start = 0x07000000,
165  .end = 0x07000000 + SZ_2M - 1,
166  .flags = IORESOURCE_MEM,
167  },
168 };
169 
170 static struct platform_device s1d13806_device = {
171  .name = "s1d13806fb",
172  .id = -1,
173  .num_resources = ARRAY_SIZE(s1d13806_resources),
174  .resource = s1d13806_resources,
175 
176  .dev = {
177  .platform_data = &s1d13806_platform_data,
178  },
179 };
180 
181 static struct platform_device *microdev_devices[] __initdata = {
182  &smc91x_device,
183  &s1d13806_device,
184 };
185 
186 static int __init microdev_devices_setup(void)
187 {
188  return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
189 }
190 device_initcall(microdev_devices_setup);
191 
192 /*
193  * The Machine Vector
194  */
195 static struct sh_machine_vector mv_sh4202_microdev __initmv = {
196  .mv_name = "SH4-202 MicroDev",
197  .mv_ioport_map = microdev_ioport_map,
198  .mv_init_irq = init_microdev_irq,
199 };
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