Go to the documentation of this file.
10 #ifndef __ASM_CPU_SH2_CACHE_H
11 #define __ASM_CPU_SH2_CACHE_H
13 #define L1_CACHE_SHIFT 4
15 #define SH_CACHE_VALID 1
16 #define SH_CACHE_UPDATED 2
17 #define SH_CACHE_COMBINED 4
18 #define SH_CACHE_ASSOC 8
20 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
21 #define CCR 0xffffffec
23 #define CCR_CACHE_CE 0x01
24 #define CCR_CACHE_WT 0x02
28 #define CCR_CACHE_CB 0x04
32 #define CCR_CACHE_CF 0x08
34 #define CACHE_OC_ADDRESS_ARRAY 0xf0000000
35 #define CACHE_OC_DATA_ARRAY 0xf1000000
37 #define CCR_CACHE_ENABLE CCR_CACHE_CE
38 #define CCR_CACHE_INVALIDATE CCR_CACHE_CF
39 #define CACHE_PHYSADDR_MASK 0x1ffffc00