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irqflags.h
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1 /*
2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation, version 2.
7  *
8  * This program is distributed in the hope that it will be useful, but
9  * WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11  * NON INFRINGEMENT. See the GNU General Public License for
12  * more details.
13  */
14 
15 #ifndef _ASM_TILE_IRQFLAGS_H
16 #define _ASM_TILE_IRQFLAGS_H
17 
18 #include <arch/interrupts.h>
19 #include <arch/chip.h>
20 
21 #if !defined(__tilegx__) && defined(__ASSEMBLY__)
22 
23 /*
24  * The set of interrupts we want to allow when interrupts are nominally
25  * disabled. The remainder are effectively "NMI" interrupts from
26  * the point of view of the generic Linux code. Note that synchronous
27  * interrupts (aka "non-queued") are not blocked by the mask in any case.
28  */
29 #if CHIP_HAS_AUX_PERF_COUNTERS()
30 #define LINUX_MASKABLE_INTERRUPTS_HI \
31  (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
32 #else
33 #define LINUX_MASKABLE_INTERRUPTS_HI \
34  (~(INT_MASK_HI(INT_PERF_COUNT)))
35 #endif
36 
37 #else
38 
39 #if CHIP_HAS_AUX_PERF_COUNTERS()
40 #define LINUX_MASKABLE_INTERRUPTS \
41  (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
42 #else
43 #define LINUX_MASKABLE_INTERRUPTS \
44  (~(INT_MASK(INT_PERF_COUNT)))
45 #endif
46 
47 #endif
48 
49 #ifndef __ASSEMBLY__
50 
51 /* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
52 #include <asm/percpu.h>
53 #include <arch/spr_def.h>
54 
55 /* Set and clear kernel interrupt masks. */
56 #if CHIP_HAS_SPLIT_INTR_MASK()
57 #if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32 || INT_MEM_ERROR >= 32
58 # error Fix assumptions about which word various interrupts are in
59 #endif
60 #define interrupt_mask_set(n) do { \
61  int __n = (n); \
62  int __mask = 1 << (__n & 0x1f); \
63  if (__n < 32) \
64  __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
65  else \
66  __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
67 } while (0)
68 #define interrupt_mask_reset(n) do { \
69  int __n = (n); \
70  int __mask = 1 << (__n & 0x1f); \
71  if (__n < 32) \
72  __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
73  else \
74  __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
75 } while (0)
76 #define interrupt_mask_check(n) ({ \
77  int __n = (n); \
78  (((__n < 32) ? \
79  __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
80  __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
81  >> (__n & 0x1f)) & 1; \
82 })
83 #define interrupt_mask_set_mask(mask) do { \
84  unsigned long long __m = (mask); \
85  __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
86  __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
87 } while (0)
88 #define interrupt_mask_reset_mask(mask) do { \
89  unsigned long long __m = (mask); \
90  __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
91  __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
92 } while (0)
93 #define interrupt_mask_save_mask() \
94  (__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_0) | \
95  (((unsigned long long)__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_1))<<32))
96 #define interrupt_mask_restore_mask(mask) do { \
97  unsigned long long __m = (mask); \
98  __insn_mtspr(SPR_INTERRUPT_MASK_K_0, (unsigned long)(__m)); \
99  __insn_mtspr(SPR_INTERRUPT_MASK_K_1, (unsigned long)(__m>>32)); \
100 } while (0)
101 #else
102 #define interrupt_mask_set(n) \
103  __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
104 #define interrupt_mask_reset(n) \
105  __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
106 #define interrupt_mask_check(n) \
107  ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
108 #define interrupt_mask_set_mask(mask) \
109  __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
110 #define interrupt_mask_reset_mask(mask) \
111  __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
112 #define interrupt_mask_save_mask() \
113  __insn_mfspr(SPR_INTERRUPT_MASK_K)
114 #define interrupt_mask_restore_mask(mask) \
115  __insn_mtspr(SPR_INTERRUPT_MASK_K, (mask))
116 #endif
117 
118 /*
119  * The set of interrupts we want active if irqs are enabled.
120  * Note that in particular, the tile timer interrupt comes and goes
121  * from this set, since we have no other way to turn off the timer.
122  * Likewise, INTCTRL_K is removed and re-added during device
123  * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
124  * We use a low bit (MEM_ERROR) as our sentinel value and make sure it
125  * is always claimed as an "active interrupt" so we can query that bit
126  * to know our current state.
127  */
128 DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
129 #define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
130 
131 /* Disable interrupts. */
132 #define arch_local_irq_disable() \
133  interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
134 
135 /* Disable all interrupts, including NMIs. */
136 #define arch_local_irq_disable_all() \
137  interrupt_mask_set_mask(-1ULL)
138 
139 /* Re-enable all maskable interrupts. */
140 #define arch_local_irq_enable() \
141  interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask))
142 
143 /* Disable or enable interrupts based on flag argument. */
144 #define arch_local_irq_restore(disabled) do { \
145  if (disabled) \
146  arch_local_irq_disable(); \
147  else \
148  arch_local_irq_enable(); \
149 } while (0)
150 
151 /* Return true if "flags" argument means interrupts are disabled. */
152 #define arch_irqs_disabled_flags(flags) ((flags) != 0)
153 
154 /* Return true if interrupts are currently disabled. */
155 #define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
156 
157 /* Save whether interrupts are currently disabled. */
158 #define arch_local_save_flags() arch_irqs_disabled()
159 
160 /* Save whether interrupts are currently disabled, then disable them. */
161 #define arch_local_irq_save() ({ \
162  unsigned long __flags = arch_local_save_flags(); \
163  arch_local_irq_disable(); \
164  __flags; })
165 
166 /* Prevent the given interrupt from being enabled next time we enable irqs. */
167 #define arch_local_irq_mask(interrupt) \
168  (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
169 
170 /* Prevent the given interrupt from being enabled immediately. */
171 #define arch_local_irq_mask_now(interrupt) do { \
172  arch_local_irq_mask(interrupt); \
173  interrupt_mask_set(interrupt); \
174 } while (0)
175 
176 /* Allow the given interrupt to be enabled next time we enable irqs. */
177 #define arch_local_irq_unmask(interrupt) \
178  (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
179 
180 /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
181 #define arch_local_irq_unmask_now(interrupt) do { \
182  arch_local_irq_unmask(interrupt); \
183  if (!irqs_disabled()) \
184  interrupt_mask_reset(interrupt); \
185 } while (0)
186 
187 #else /* __ASSEMBLY__ */
188 
189 /* We provide a somewhat more restricted set for assembly. */
190 
191 #ifdef __tilegx__
192 
193 #if INT_MEM_ERROR != 0
194 # error Fix IRQS_DISABLED() macro
195 #endif
196 
197 /* Return 0 or 1 to indicate whether interrupts are currently disabled. */
198 #define IRQS_DISABLED(tmp) \
199  mfspr tmp, SPR_INTERRUPT_MASK_K; \
200  andi tmp, tmp, 1
201 
202 /* Load up a pointer to &interrupts_enabled_mask. */
203 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
204  moveli reg, hw2_last(interrupts_enabled_mask); \
205  shl16insli reg, reg, hw1(interrupts_enabled_mask); \
206  shl16insli reg, reg, hw0(interrupts_enabled_mask); \
207  add reg, reg, tp
208 
209 /* Disable interrupts. */
210 #define IRQ_DISABLE(tmp0, tmp1) \
211  moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \
212  shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \
213  shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \
214  mtspr SPR_INTERRUPT_MASK_SET_K, tmp0
215 
216 /* Disable ALL synchronous interrupts (used by NMI entry). */
217 #define IRQ_DISABLE_ALL(tmp) \
218  movei tmp, -1; \
219  mtspr SPR_INTERRUPT_MASK_SET_K, tmp
220 
221 /* Enable interrupts. */
222 #define IRQ_ENABLE_LOAD(tmp0, tmp1) \
223  GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
224  ld tmp0, tmp0
225 #define IRQ_ENABLE_APPLY(tmp0, tmp1) \
226  mtspr SPR_INTERRUPT_MASK_RESET_K, tmp0
227 
228 #else /* !__tilegx__ */
229 
230 /*
231  * Return 0 or 1 to indicate whether interrupts are currently disabled.
232  * Note that it's important that we use a bit from the "low" mask word,
233  * since when we are enabling, that is the word we write first, so if we
234  * are interrupted after only writing half of the mask, the interrupt
235  * handler will correctly observe that we have interrupts enabled, and
236  * will enable interrupts itself on return from the interrupt handler
237  * (making the original code's write of the "high" mask word idempotent).
238  */
239 #define IRQS_DISABLED(tmp) \
240  mfspr tmp, SPR_INTERRUPT_MASK_K_0; \
241  shri tmp, tmp, INT_MEM_ERROR; \
242  andi tmp, tmp, 1
243 
244 /* Load up a pointer to &interrupts_enabled_mask. */
245 #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
246  moveli reg, lo16(interrupts_enabled_mask); \
247  auli reg, reg, ha16(interrupts_enabled_mask); \
248  add reg, reg, tp
249 
250 /* Disable interrupts. */
251 #define IRQ_DISABLE(tmp0, tmp1) \
252  { \
253  movei tmp0, -1; \
254  moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
255  }; \
256  { \
257  mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp0; \
258  auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI) \
259  }; \
260  mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1
261 
262 /* Disable ALL synchronous interrupts (used by NMI entry). */
263 #define IRQ_DISABLE_ALL(tmp) \
264  movei tmp, -1; \
265  mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp; \
266  mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp
267 
268 /* Enable interrupts. */
269 #define IRQ_ENABLE_LOAD(tmp0, tmp1) \
270  GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
271  { \
272  lw tmp0, tmp0; \
273  addi tmp1, tmp0, 4 \
274  }; \
275  lw tmp1, tmp1
276 #define IRQ_ENABLE_APPLY(tmp0, tmp1) \
277  mtspr SPR_INTERRUPT_MASK_RESET_K_0, tmp0; \
278  mtspr SPR_INTERRUPT_MASK_RESET_K_1, tmp1
279 #endif
280 
281 #define IRQ_ENABLE(tmp0, tmp1) \
282  IRQ_ENABLE_LOAD(tmp0, tmp1); \
283  IRQ_ENABLE_APPLY(tmp0, tmp1)
284 
285 /*
286  * Do the CPU's IRQ-state tracing from assembly code. We call a
287  * C function, but almost everywhere we do, we don't mind clobbering
288  * all the caller-saved registers.
289  */
290 #ifdef CONFIG_TRACE_IRQFLAGS
291 # define TRACE_IRQS_ON jal trace_hardirqs_on
292 # define TRACE_IRQS_OFF jal trace_hardirqs_off
293 #else
294 # define TRACE_IRQS_ON
295 # define TRACE_IRQS_OFF
296 #endif
297 
298 #endif /* __ASSEMBLY__ */
299 
300 #endif /* _ASM_TILE_IRQFLAGS_H */
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