1 #ifndef __KVM_X86_MMU_H
2 #define __KVM_X86_MMU_H
8 #define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
9 #define PT32_PT_BITS 10
10 #define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
12 #define PT_WRITABLE_SHIFT 1
14 #define PT_PRESENT_MASK (1ULL << 0)
15 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
16 #define PT_USER_MASK (1ULL << 2)
17 #define PT_PWT_MASK (1ULL << 3)
18 #define PT_PCD_MASK (1ULL << 4)
19 #define PT_ACCESSED_SHIFT 5
20 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
21 #define PT_DIRTY_SHIFT 6
22 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
23 #define PT_PAGE_SIZE_SHIFT 7
24 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
25 #define PT_PAT_MASK (1ULL << 7)
26 #define PT_GLOBAL_MASK (1ULL << 8)
27 #define PT64_NX_SHIFT 63
28 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
30 #define PT_PAT_SHIFT 7
31 #define PT_DIR_PAT_SHIFT 12
32 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
34 #define PT32_DIR_PSE36_SIZE 4
35 #define PT32_DIR_PSE36_SHIFT 13
36 #define PT32_DIR_PSE36_MASK \
37 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
39 #define PT64_ROOT_LEVEL 4
40 #define PT32_ROOT_LEVEL 2
41 #define PT32E_ROOT_LEVEL 3
43 #define PT_PDPE_LEVEL 3
44 #define PT_DIRECTORY_LEVEL 2
45 #define PT_PAGE_TABLE_LEVEL 1
47 #define PFERR_PRESENT_MASK (1U << 0)
48 #define PFERR_WRITE_MASK (1U << 1)
49 #define PFERR_USER_MASK (1U << 2)
50 #define PFERR_RSVD_MASK (1U << 3)
51 #define PFERR_FETCH_MASK (1U << 4)
58 static inline unsigned int kvm_mmu_available_pages(
struct kvm *
kvm)
60 return kvm->
arch.n_max_mmu_pages -
61 kvm->
arch.n_used_mmu_pages;
64 static inline void kvm_mmu_free_some_pages(
struct kvm_vcpu *vcpu)
70 static inline int kvm_mmu_reload(
struct kvm_vcpu *vcpu)
78 static inline int is_present_gpte(
unsigned long pte)
83 static inline int is_writable_pte(
unsigned long pte)
88 static inline bool is_write_protection(
struct kvm_vcpu *vcpu)
97 static inline bool permission_fault(
struct kvm_mmu *mmu,
unsigned pte_access,
100 return (mmu->
permissions[pfec >> 1] >> pte_access) & 1;