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14 #include <asm/cache.h>
17 #if (DCACHE_WAY_SIZE <= PAGE_SIZE)
21 # define tlb_start_vma(tlb,vma) do { } while (0)
22 # define tlb_end_vma(tlb,vma) do { } while (0)
26 # define tlb_start_vma(tlb, vma) \
29 flush_cache_range(vma, vma->vm_start, vma->vm_end); \
32 # define tlb_end_vma(tlb, vma) \
35 flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
40 #define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
41 #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
45 #define __pte_free_tlb(tlb, pte, address) pte_free((tlb)->mm, pte)