Linux Kernel  3.7.1
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intc.h
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1 #ifndef __ASM_MACH_INTC_H
2 #define __ASM_MACH_INTC_H
3 #include <linux/sh_intc.h>
4 
5 #define INTC_IRQ_PINS_ENUM_16L(p) \
6  p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
7  p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \
8  p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
9  p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15
10 
11 #define INTC_IRQ_PINS_ENUM_16H(p) \
12  p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
13  p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \
14  p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
15  p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31
16 
17 #define INTC_IRQ_PINS_VECT_16L(p, vect) \
18  vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \
19  vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \
20  vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \
21  vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \
22  vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \
23  vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \
24  vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \
25  vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0)
26 
27 #define INTC_IRQ_PINS_VECT_16H(p, vect) \
28  vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \
29  vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \
30  vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \
31  vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \
32  vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \
33  vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \
34  vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \
35  vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0)
36 
37 #define INTC_IRQ_PINS_MASK_16L(p, base) \
38  { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \
39  { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
40  p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
41  { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \
42  { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
43  p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
44 
45 #define INTC_IRQ_PINS_MASK_16H(p, base) \
46  { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \
47  { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
48  p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
49  { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \
50  { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
51  p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
52 
53 #define INTC_IRQ_PINS_PRIO_16L(p, base) \
54  { base + 0x10, 0, 32, 4, /* INTPRI00A */ \
55  { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
56  p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
57  { base + 0x14, 0, 32, 4, /* INTPRI10A */ \
58  { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
59  p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
60 
61 #define INTC_IRQ_PINS_PRIO_16H(p, base) \
62  { base + 0x18, 0, 32, 4, /* INTPRI20A */ \
63  { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
64  p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
65  { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \
66  { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
67  p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
68 
69 #define INTC_IRQ_PINS_SENSE_16L(p, base) \
70  { base + 0x00, 32, 4, /* ICR1A */ \
71  { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
72  p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
73  { base + 0x04, 32, 4, /* ICR2A */ \
74  { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
75  p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
76 
77 #define INTC_IRQ_PINS_SENSE_16H(p, base) \
78  { base + 0x08, 32, 4, /* ICR3A */ \
79  { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
80  p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
81  { base + 0x0c, 32, 4, /* ICR4A */ \
82  { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
83  p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
84 
85 #define INTC_IRQ_PINS_ACK_16L(p, base) \
86  { base + 0x20, 0, 8, /* INTREQ00A */ \
87  { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
88  p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
89  { base + 0x24, 0, 8, /* INTREQ10A */ \
90  { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
91  p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
92 
93 #define INTC_IRQ_PINS_ACK_16H(p, base) \
94  { base + 0x28, 0, 8, /* INTREQ20A */ \
95  { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
96  p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
97  { base + 0x2c, 0, 8, /* INTREQ30A */ \
98  { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
99  p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
100 
101 #define INTC_IRQ_PINS_16(p, base, vect, str) \
102  \
103 static struct resource p ## _resources[] __initdata = { \
104  [0] = { \
105  .start = base, \
106  .end = base + 0x64, \
107  .flags = IORESOURCE_MEM, \
108  }, \
109 }; \
110  \
111 enum { \
112  p ## _UNUSED = 0, \
113  INTC_IRQ_PINS_ENUM_16L(p), \
114 }; \
115  \
116 static struct intc_vect p ## _vectors[] __initdata = { \
117  INTC_IRQ_PINS_VECT_16L(p, vect), \
118 }; \
119  \
120 static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
121  INTC_IRQ_PINS_MASK_16L(p, base), \
122 }; \
123  \
124 static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
125  INTC_IRQ_PINS_PRIO_16L(p, base), \
126 }; \
127  \
128 static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
129  INTC_IRQ_PINS_SENSE_16L(p, base), \
130 }; \
131  \
132 static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
133  INTC_IRQ_PINS_ACK_16L(p, base), \
134 }; \
135  \
136 static struct intc_desc p ## _desc __initdata = { \
137  .name = str, \
138  .resource = p ## _resources, \
139  .num_resources = ARRAY_SIZE(p ## _resources), \
140  .hw = INTC_HW_DESC(p ## _vectors, NULL, \
141  p ## _mask_registers, p ## _prio_registers, \
142  p ## _sense_registers, p ## _ack_registers) \
143 }
144 
145 #define INTC_IRQ_PINS_16H(p, base, vect, str) \
146  \
147 static struct resource p ## _resources[] __initdata = { \
148  [0] = { \
149  .start = base, \
150  .end = base + 0x64, \
151  .flags = IORESOURCE_MEM, \
152  }, \
153 }; \
154  \
155 enum { \
156  p ## _UNUSED = 0, \
157  INTC_IRQ_PINS_ENUM_16H(p), \
158 }; \
159  \
160 static struct intc_vect p ## _vectors[] __initdata = { \
161  INTC_IRQ_PINS_VECT_16H(p, vect), \
162 }; \
163  \
164 static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
165  INTC_IRQ_PINS_MASK_16H(p, base), \
166 }; \
167  \
168 static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
169  INTC_IRQ_PINS_PRIO_16H(p, base), \
170 }; \
171  \
172 static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
173  INTC_IRQ_PINS_SENSE_16H(p, base), \
174 }; \
175  \
176 static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
177  INTC_IRQ_PINS_ACK_16H(p, base), \
178 }; \
179  \
180 static struct intc_desc p ## _desc __initdata = { \
181  .name = str, \
182  .resource = p ## _resources, \
183  .num_resources = ARRAY_SIZE(p ## _resources), \
184  .hw = INTC_HW_DESC(p ## _vectors, NULL, \
185  p ## _mask_registers, p ## _prio_registers, \
186  p ## _sense_registers, p ## _ack_registers) \
187 }
188 
189 #define INTC_IRQ_PINS_32(p, base, vect, str) \
190  \
191 static struct resource p ## _resources[] __initdata = { \
192  [0] = { \
193  .start = base, \
194  .end = base + 0x6c, \
195  .flags = IORESOURCE_MEM, \
196  }, \
197 }; \
198  \
199 enum { \
200  p ## _UNUSED = 0, \
201  INTC_IRQ_PINS_ENUM_16L(p), \
202  INTC_IRQ_PINS_ENUM_16H(p), \
203 }; \
204  \
205 static struct intc_vect p ## _vectors[] __initdata = { \
206  INTC_IRQ_PINS_VECT_16L(p, vect), \
207  INTC_IRQ_PINS_VECT_16H(p, vect), \
208 }; \
209  \
210 static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
211  INTC_IRQ_PINS_MASK_16L(p, base), \
212  INTC_IRQ_PINS_MASK_16H(p, base), \
213 }; \
214  \
215 static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
216  INTC_IRQ_PINS_PRIO_16L(p, base), \
217  INTC_IRQ_PINS_PRIO_16H(p, base), \
218 }; \
219  \
220 static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
221  INTC_IRQ_PINS_SENSE_16L(p, base), \
222  INTC_IRQ_PINS_SENSE_16H(p, base), \
223 }; \
224  \
225 static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
226  INTC_IRQ_PINS_ACK_16L(p, base), \
227  INTC_IRQ_PINS_ACK_16H(p, base), \
228 }; \
229  \
230 static struct intc_desc p ## _desc __initdata = { \
231  .name = str, \
232  .resource = p ## _resources, \
233  .num_resources = ARRAY_SIZE(p ## _resources), \
234  .hw = INTC_HW_DESC(p ## _vectors, NULL, \
235  p ## _mask_registers, p ## _prio_registers, \
236  p ## _sense_registers, p ## _ack_registers) \
237 }
238 
239 #define INTC_PINT_E_EMPTY
240 #define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0,
241 #define INTC_PINT_E(p) \
242  PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \
243  PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7,
244 
245 #define INTC_PINT_V_NONE
246 #define INTC_PINT_V(p, vect) \
247  vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \
248  vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \
249  vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \
250  vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7),
251 
252 #define INTC_PINT(p, mask_reg, sense_base, str, \
253  enums_1, enums_2, enums_3, enums_4, \
254  vect_1, vect_2, vect_3, vect_4, \
255  mask_a, mask_b, mask_c, mask_d, \
256  sense_a, sense_b, sense_c, sense_d) \
257  \
258 enum { \
259  PINT ## p ## _UNUSED = 0, \
260  enums_1 enums_2 enums_3 enums_4 \
261 }; \
262  \
263 static struct intc_vect p ## _vectors[] __initdata = { \
264  vect_1 vect_2 vect_3 vect_4 \
265 }; \
266  \
267 static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
268  { mask_reg, 0, 32, /* PINTER */ \
269  { mask_a mask_b mask_c mask_d } } \
270 }; \
271  \
272 static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
273  { sense_base + 0x00, 16, 2, /* PINTCR */ \
274  { sense_a } }, \
275  { sense_base + 0x04, 16, 2, /* PINTCR */ \
276  { sense_b } }, \
277  { sense_base + 0x08, 16, 2, /* PINTCR */ \
278  { sense_c } }, \
279  { sense_base + 0x0c, 16, 2, /* PINTCR */ \
280  { sense_d } }, \
281 }; \
282  \
283 static struct intc_desc p ## _desc __initdata = { \
284  .name = str, \
285  .hw = INTC_HW_DESC(p ## _vectors, NULL, \
286  p ## _mask_registers, NULL, \
287  p ## _sense_registers, NULL), \
288 }
289 
290 #endif /* __ASM_MACH_INTC_H */
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