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atarihw.h
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1 /*
2 ** linux/atarihw.h -- This header defines some macros and pointers for
3 ** the various Atari custom hardware registers.
4 **
5 ** Copyright 1994 by Björn Brauel
6 **
7 ** 5/1/94 Roman Hodek:
8 ** Added definitions for TT specific chips.
9 **
10 ** 1996-09-13 lars brinkhoff <[email protected]>:
11 ** Finally added definitions for the matrix/codec and the DSP56001 host
12 ** interface.
13 **
14 ** This file is subject to the terms and conditions of the GNU General Public
15 ** License. See the file COPYING in the main directory of this archive
16 ** for more details.
17 **
18 */
19 
20 #ifndef _LINUX_ATARIHW_H_
21 #define _LINUX_ATARIHW_H_
22 
23 #include <linux/types.h>
24 #include <asm/bootinfo.h>
25 #include <asm/raw_io.h>
26 
28 extern u_long atari_mch_type;
29 extern u_long atari_switches;
30 extern int atari_rtc_year_offset;
32 
33 extern int atari_SCC_reset_done;
34 
35 /* convenience macros for testing machine type */
36 #define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
37 #define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
38  (atari_mch_cookie & 0xffff) == 0)
39 #define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
40  (atari_mch_cookie & 0xffff) == 0x10)
41 #define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
42 #define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
43 #define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
44 #define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
45 
46 /* values for atari_switches */
47 #define ATARI_SWITCH_IKBD 0x01
48 #define ATARI_SWITCH_MIDI 0x02
49 #define ATARI_SWITCH_SND6 0x04
50 #define ATARI_SWITCH_SND7 0x08
51 #define ATARI_SWITCH_OVSC_SHIFT 16
52 #define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
53 #define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
54 #define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
55 #define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
56 #define ATARI_SWITCH_OVSC_MASK 0xffff0000
57 
58 /*
59  * Define several Hardware-Chips for indication so that for the ATARI we do
60  * no longer decide whether it is a Falcon or other machine . It's just
61  * important what hardware the machine uses
62  */
63 
64 /* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
65 
66 #define ATARIHW_DECLARE(name) unsigned name : 1
67 #define ATARIHW_SET(name) (atari_hw_present.name = 1)
68 #define ATARIHW_PRESENT(name) (atari_hw_present.name)
69 
71  /* video hardware */
72  ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
73  ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
74  ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
75  ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
76  /* sound hardware */
77  ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
78  ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
79  ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
80  /* disk storage interfaces */
81  ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
82  ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
83  ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
84  ATARIHW_DECLARE(IDE); /* IDE Interface */
85  ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
86  /* other I/O hardware */
87  ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari
88  without it... but who knows?) */
89  ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
90  ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
91  ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
92  ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
93  and Falcon */
94  ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
95  /* DMA */
96  ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
97  ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
98  ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
99  ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
100  /* real time clocks */
101  ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
102  ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
103  /* supporting hardware */
104  ATARIHW_DECLARE(SCU); /* System Control Unit */
105  ATARIHW_DECLARE(BLITTER); /* Blitter */
106  ATARIHW_DECLARE(VME); /* VME Bus */
107  ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */
108 };
109 
110 extern struct atari_hw_present atari_hw_present;
111 
112 
113 /* Reading the MFP port register gives a machine independent delay, since the
114  * MFP always has a 8 MHz clock. This avoids problems with the varying length
115  * of nops on various machines. Somebody claimed that the tstb takes 600 ns.
116  */
117 #define MFPDELAY() \
118  __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" );
119 
120 /* Do cache push/invalidate for DMA read/write. This function obeys the
121  * snooping on some machines (Medusa) and processors: The Medusa itself can
122  * snoop, but only the '040 can source data from its cache to DMA writes i.e.,
123  * reads from memory). Both '040 and '060 invalidate cache entries on snooped
124  * DMA reads (i.e., writes to memory).
125  */
126 
127 
128 #define atari_readb raw_inb
129 #define atari_writeb raw_outb
130 
131 #define atari_inb_p raw_inb
132 #define atari_outb_p raw_outb
133 
134 
135 
136 #include <linux/mm.h>
137 #include <asm/cacheflush.h>
138 
139 static inline void dma_cache_maintenance( unsigned long paddr,
140  unsigned long len,
141  int writeflag )
142 
143 {
144  if (writeflag) {
145  if (!MACH_IS_MEDUSA || CPU_IS_060)
146  cache_push( paddr, len );
147  }
148  else {
149  if (!MACH_IS_MEDUSA)
150  cache_clear( paddr, len );
151  }
152 }
153 
154 
155 /*
156 ** Shifter
157  */
158 #define ST_LOW 0
159 #define ST_MID 1
160 #define ST_HIGH 2
161 #define TT_LOW 7
162 #define TT_MID 4
163 #define TT_HIGH 6
164 
165 #define SHF_BAS (0xffff8200)
166 struct SHIFTER
167  {
173  u_char volatile vcounthi;
175  u_char volatile vcountmid;
177  u_char volatile vcountlow;
178  u_char volatile syncmode;
182  };
183 # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
184 
185 #define SHF_FBAS (0xffff820e)
187  {
190  };
191 # define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
192 
193 
194 #define SHF_TBAS (0xffff8200)
195 struct SHIFTER_TT {
197  u_char bas_hi; /* video mem base addr, high and mid byte */
201  u_char vcount_hi; /* pointer to currently displayed byte */
206  u_short st_sync; /* ST compatible sync mode register, unused */
208  u_char bas_lo; /* video mem addr, low byte */
210  /* $ffff8240: */
211  u_short color_reg[16]; /* 16 color registers */
212  u_char st_shiftmode; /* ST compatible shift mode register, unused */
214  u_short tt_shiftmode; /* TT shift mode register */
215 
216 
217 };
218 #define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
219 
220 /* values for shifter_tt->tt_shiftmode */
221 #define TT_SHIFTER_STLOW 0x0000
222 #define TT_SHIFTER_STMID 0x0100
223 #define TT_SHIFTER_STHIGH 0x0200
224 #define TT_SHIFTER_TTLOW 0x0700
225 #define TT_SHIFTER_TTMID 0x0400
226 #define TT_SHIFTER_TTHIGH 0x0600
227 #define TT_SHIFTER_MODEMASK 0x0700
228 #define TT_SHIFTER_NUMMODE 0x0008
229 #define TT_SHIFTER_PALETTE_MASK 0x000f
230 #define TT_SHIFTER_GRAYMODE 0x1000
231 
232 /* 256 TT palette registers */
233 #define TT_PALETTE_BASE (0xffff8400)
234 #define tt_palette ((volatile u_short *)TT_PALETTE_BASE)
235 
236 #define TT_PALETTE_RED_MASK 0x0f00
237 #define TT_PALETTE_GREEN_MASK 0x00f0
238 #define TT_PALETTE_BLUE_MASK 0x000f
239 
240 /*
241 ** Falcon030 VIDEL Video Controller
242 ** for description see File 'linux\tools\atari\hardware.txt
243  */
244 #define f030_col ((u_long *) 0xffff9800)
245 #define f030_xreg ((u_short*) 0xffff8282)
246 #define f030_yreg ((u_short*) 0xffff82a2)
247 #define f030_creg ((u_short*) 0xffff82c0)
248 #define f030_sreg ((u_short*) 0xffff8260)
249 #define f030_mreg ((u_short*) 0xffff820a)
250 #define f030_linewidth ((u_short*) 0xffff820e)
251 #define f030_hscroll ((u_char*) 0xffff8265)
252 
253 #define VIDEL_BAS (0xffff8260)
254 struct VIDEL {
260  u_char pad2[0x1a];
267  u_char pad3[0x14];
274  u_char pad4[0x12];
277 };
278 #define videl ((*(volatile struct VIDEL *)VIDEL_BAS))
279 
280 /*
281 ** DMA/WD1772 Disk Controller
282  */
283 
284 #define FWD_BAS (0xffff8604)
285 struct DMA_WD
286  {
289  u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */
296  };
297 # define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
298 /* alias */
299 #define st_dma dma_wd
300 /* The two highest bytes of an extended DMA as a short; this is a must
301  * for the Medusa.
302  */
303 #define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
304 
305 /*
306 ** YM2149 Sound Chip
307 ** access in bytes
308  */
309 
310 #define YM_BAS (0xffff8800)
311 struct SOUND_YM
312  {
316  };
317 #define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
318 
319 /* TT SCSI DMA */
320 
321 #define TT_SCSI_DMA_BAS (0xffff8700)
322 struct TT_DMA {
341 };
342 #define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
343 
344 /* TT SCSI Controller 5380 */
345 
346 #define TT_5380_BAS (0xffff8781)
347 struct TT_5380 {
363 };
364 #define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS))
365 #define tt_scsi_regp ((volatile char *)TT_5380_BAS)
366 
367 
368 /*
369 ** Falcon DMA Sound Subsystem
370  */
371 
372 #define MATRIX_BASE (0xffff8930)
373 struct MATRIX
374 {
379 };
380 #define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE)
381 
382 #define CODEC_BASE (0xffff8936)
383 struct CODEC
384 {
387 #define CODEC_SOURCE_ADC 1
388 #define CODEC_SOURCE_MATRIX 2
390 #define ADC_SOURCE_RIGHT_PSG 1
391 #define ADC_SOURCE_LEFT_PSG 2
393 #define CODEC_GAIN_RIGHT 0x0f
394 #define CODEC_GAIN_LEFT 0xf0
396 #define CODEC_ATTENUATION_RIGHT 0x0f
397 #define CODEC_ATTENUATION_LEFT 0xf0
400 #define CODEC_OVERFLOW_RIGHT 1
401 #define CODEC_OVERFLOW_LEFT 2
404 #define CODEC_GPIO_IN 0
405 #define CODEC_GPIO_OUT 1
408 };
409 #define falcon_codec (*(volatile struct CODEC *)CODEC_BASE)
410 
411 /*
412 ** Falcon Blitter
413 */
414 
415 #define BLT_BAS (0xffff8a00)
416 
417 struct BLITTER
418  {
435  };
436 # define blitter ((*(volatile struct BLITTER *)BLT_BAS))
437 
438 
439 /*
440 ** SCC Z8530
441  */
442 
443 #define SCC_BAS (0xffff8c81)
444 struct SCC
445  {
453  };
454 # define atari_scc ((*(volatile struct SCC*)SCC_BAS))
455 
456 /* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
457 # define st_escc ((*(volatile struct SCC*)0xfffffa31))
458 # define st_escc_dsr ((*(volatile char *)0xfffffa39))
459 
460 /* TT SCC DMA Controller (same chip as SCSI DMA) */
461 
462 #define TT_SCC_DMA_BAS (0xffff8c00)
463 #define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
464 
465 /*
466 ** VIDEL Palette Register
467  */
468 
469 #define FPL_BAS (0xffff9800)
471  {
472  u_long reg[256];
473  };
474 # define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
475 
476 
477 /*
478 ** Falcon DSP Host Interface
479  */
480 
481 #define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
484 #define DSP56K_ICR_RREQ 0x01
485 #define DSP56K_ICR_TREQ 0x02
486 #define DSP56K_ICR_HF0 0x08
487 #define DSP56K_ICR_HF1 0x10
488 #define DSP56K_ICR_HM0 0x20
489 #define DSP56K_ICR_HM1 0x40
490 #define DSP56K_ICR_INIT 0x80
491 
493 #define DSP56K_CVR_HV_MASK 0x1f
494 #define DSP56K_CVR_HC 0x80
495 
497 #define DSP56K_ISR_RXDF 0x01
498 #define DSP56K_ISR_TXDE 0x02
499 #define DSP56K_ISR_TRDY 0x04
500 #define DSP56K_ISR_HF2 0x08
501 #define DSP56K_ISR_HF3 0x10
502 #define DSP56K_ISR_DMA 0x40
503 #define DSP56K_ISR_HREQ 0x80
504 
506 
507  union {
508  u_char b[4];
509  u_short w[2];
511  } data;
512 };
513 #define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
514 
515 /*
516 ** MFP 68901
517  */
518 
519 #define MFP_BAS (0xfffffa01)
520 struct MFP
521  {
569  };
570 # define st_mfp ((*(volatile struct MFP*)MFP_BAS))
571 
572 /* TT's second MFP */
573 
574 #define TT_MFP_BAS (0xfffffa81)
575 # define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
576 
577 
578 /* TT System Control Unit */
579 
580 #define TT_SCU_BAS (0xffff8e01)
581 struct TT_SCU {
597 };
598 #define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS))
599 
600 /* TT real time clock */
601 
602 #define TT_RTC_BAS (0xffff8961)
603 struct TT_RTC {
607 };
608 #define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS))
609 
610 
611 /*
612 ** ACIA 6850
613  */
614 /* constants for the ACIA registers */
615 
616 /* baudrate selection and reset (Baudrate = clock/factor) */
617 #define ACIA_DIV1 0
618 #define ACIA_DIV16 1
619 #define ACIA_DIV64 2
620 #define ACIA_RESET 3
621 
622 /* character format */
623 #define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */
624 #define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */
625 #define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */
626 #define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */
627 #define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */
628 #define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */
629 #define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */
630 #define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */
631 
632 /* transmit control */
633 #define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */
634 #define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */
635 #define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */
636 #define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */
637 
638 /* receive control */
639 #define ACIA_RID (0<<7) /* RxINT disabled */
640 #define ACIA_RIE (1<<7) /* RxINT enabled */
641 
642 /* status fields of the ACIA */
643 #define ACIA_RDRF 1 /* Receive Data Register Full */
644 #define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */
645 #define ACIA_DCD (1<<2) /* Data Carrier Detect */
646 #define ACIA_CTS (1<<3) /* Clear To Send */
647 #define ACIA_FE (1<<4) /* Framing Error */
648 #define ACIA_OVRN (1<<5) /* Receiver Overrun */
649 #define ACIA_PE (1<<6) /* Parity Error */
650 #define ACIA_IRQ (1<<7) /* Interrupt Request */
651 
652 #define ACIA_BAS (0xfffffc00)
653 struct ACIA
654  {
662  };
663 # define acia ((*(volatile struct ACIA*)ACIA_BAS))
664 
665 #define TT_DMASND_BAS (0xffff8900)
666 struct TT_DMASND {
667  u_char int_ctrl; /* Falcon: Interrupt control */
688  u_char track_select; /* Falcon */
691  /* Falcon only: */
701 };
702 # define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
703 
704 #define DMASND_MFP_INT_REPLAY 0x01
705 #define DMASND_MFP_INT_RECORD 0x02
706 #define DMASND_TIMERA_INT_REPLAY 0x04
707 #define DMASND_TIMERA_INT_RECORD 0x08
708 
709 #define DMASND_CTRL_OFF 0x00
710 #define DMASND_CTRL_ON 0x01
711 #define DMASND_CTRL_REPEAT 0x02
712 #define DMASND_CTRL_RECORD_ON 0x10
713 #define DMASND_CTRL_RECORD_OFF 0x00
714 #define DMASND_CTRL_RECORD_REPEAT 0x20
715 #define DMASND_CTRL_SELECT_REPLAY 0x00
716 #define DMASND_CTRL_SELECT_RECORD 0x80
717 #define DMASND_MODE_MONO 0x80
718 #define DMASND_MODE_STEREO 0x00
719 #define DMASND_MODE_8BIT 0x00
720 #define DMASND_MODE_16BIT 0x40 /* Falcon only */
721 #define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */
722 #define DMASND_MODE_12KHZ 0x01
723 #define DMASND_MODE_25KHZ 0x02
724 #define DMASND_MODE_50KHZ 0x03
725 
726 
727 #define DMASNDSetBase(bufstart) \
728  do { \
729  tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
730  tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
731  tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
732  } while( 0 )
733 
734 #define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \
735  (tt_dmasnd.addr_mid << 8) + \
736  (tt_dmasnd.addr_low))
737 
738 #define DMASNDSetEnd(bufend) \
739  do { \
740  tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \
741  tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
742  tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
743  } while( 0 )
744 
745 
746 #define TT_MICROWIRE_BAS (0xffff8922)
747 struct TT_MICROWIRE {
750 };
751 # define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
752 
753 #define MW_LM1992_ADDR 0x0400
754 
755 #define MW_LM1992_VOLUME(dB) \
756  (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
757 #define MW_LM1992_BALLEFT(dB) \
758  (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
759 #define MW_LM1992_BALRIGHT(dB) \
760  (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
761 #define MW_LM1992_TREBLE(dB) \
762  (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
763 #define MW_LM1992_BASS(dB) \
764  (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
765 
766 #define MW_LM1992_PSG_LOW 0x000
767 #define MW_LM1992_PSG_HIGH 0x001
768 #define MW_LM1992_PSG_OFF 0x002
769 
770 #define MSTE_RTC_BAS (0xfffffc21)
771 
772 struct MSTE_RTC {
804 };
805 
806 #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
807 
808 #endif /* linux/atarihw.h */
809