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atmel-ssc.h
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1 #ifndef __INCLUDE_ATMEL_SSC_H
2 #define __INCLUDE_ATMEL_SSC_H
3 
5 #include <linux/list.h>
6 #include <linux/io.h>
7 
8 struct ssc_device {
9  struct list_head list;
10  void __iomem *regs;
12  struct clk *clk;
13  int user;
14  int irq;
15 };
16 
17 struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
18 void ssc_free(struct ssc_device *ssc);
19 
20 /* SSC register offsets */
21 
22 /* SSC Control Register */
23 #define SSC_CR 0x00000000
24 #define SSC_CR_RXDIS_SIZE 1
25 #define SSC_CR_RXDIS_OFFSET 1
26 #define SSC_CR_RXEN_SIZE 1
27 #define SSC_CR_RXEN_OFFSET 0
28 #define SSC_CR_SWRST_SIZE 1
29 #define SSC_CR_SWRST_OFFSET 15
30 #define SSC_CR_TXDIS_SIZE 1
31 #define SSC_CR_TXDIS_OFFSET 9
32 #define SSC_CR_TXEN_SIZE 1
33 #define SSC_CR_TXEN_OFFSET 8
34 
35 /* SSC Clock Mode Register */
36 #define SSC_CMR 0x00000004
37 #define SSC_CMR_DIV_SIZE 12
38 #define SSC_CMR_DIV_OFFSET 0
39 
40 /* SSC Receive Clock Mode Register */
41 #define SSC_RCMR 0x00000010
42 #define SSC_RCMR_CKG_SIZE 2
43 #define SSC_RCMR_CKG_OFFSET 6
44 #define SSC_RCMR_CKI_SIZE 1
45 #define SSC_RCMR_CKI_OFFSET 5
46 #define SSC_RCMR_CKO_SIZE 3
47 #define SSC_RCMR_CKO_OFFSET 2
48 #define SSC_RCMR_CKS_SIZE 2
49 #define SSC_RCMR_CKS_OFFSET 0
50 #define SSC_RCMR_PERIOD_SIZE 8
51 #define SSC_RCMR_PERIOD_OFFSET 24
52 #define SSC_RCMR_START_SIZE 4
53 #define SSC_RCMR_START_OFFSET 8
54 #define SSC_RCMR_STOP_SIZE 1
55 #define SSC_RCMR_STOP_OFFSET 12
56 #define SSC_RCMR_STTDLY_SIZE 8
57 #define SSC_RCMR_STTDLY_OFFSET 16
58 
59 /* SSC Receive Frame Mode Register */
60 #define SSC_RFMR 0x00000014
61 #define SSC_RFMR_DATLEN_SIZE 5
62 #define SSC_RFMR_DATLEN_OFFSET 0
63 #define SSC_RFMR_DATNB_SIZE 4
64 #define SSC_RFMR_DATNB_OFFSET 8
65 #define SSC_RFMR_FSEDGE_SIZE 1
66 #define SSC_RFMR_FSEDGE_OFFSET 24
67 #define SSC_RFMR_FSLEN_SIZE 4
68 #define SSC_RFMR_FSLEN_OFFSET 16
69 #define SSC_RFMR_FSOS_SIZE 4
70 #define SSC_RFMR_FSOS_OFFSET 20
71 #define SSC_RFMR_LOOP_SIZE 1
72 #define SSC_RFMR_LOOP_OFFSET 5
73 #define SSC_RFMR_MSBF_SIZE 1
74 #define SSC_RFMR_MSBF_OFFSET 7
75 
76 /* SSC Transmit Clock Mode Register */
77 #define SSC_TCMR 0x00000018
78 #define SSC_TCMR_CKG_SIZE 2
79 #define SSC_TCMR_CKG_OFFSET 6
80 #define SSC_TCMR_CKI_SIZE 1
81 #define SSC_TCMR_CKI_OFFSET 5
82 #define SSC_TCMR_CKO_SIZE 3
83 #define SSC_TCMR_CKO_OFFSET 2
84 #define SSC_TCMR_CKS_SIZE 2
85 #define SSC_TCMR_CKS_OFFSET 0
86 #define SSC_TCMR_PERIOD_SIZE 8
87 #define SSC_TCMR_PERIOD_OFFSET 24
88 #define SSC_TCMR_START_SIZE 4
89 #define SSC_TCMR_START_OFFSET 8
90 #define SSC_TCMR_STTDLY_SIZE 8
91 #define SSC_TCMR_STTDLY_OFFSET 16
92 
93 /* SSC Transmit Frame Mode Register */
94 #define SSC_TFMR 0x0000001c
95 #define SSC_TFMR_DATDEF_SIZE 1
96 #define SSC_TFMR_DATDEF_OFFSET 5
97 #define SSC_TFMR_DATLEN_SIZE 5
98 #define SSC_TFMR_DATLEN_OFFSET 0
99 #define SSC_TFMR_DATNB_SIZE 4
100 #define SSC_TFMR_DATNB_OFFSET 8
101 #define SSC_TFMR_FSDEN_SIZE 1
102 #define SSC_TFMR_FSDEN_OFFSET 23
103 #define SSC_TFMR_FSEDGE_SIZE 1
104 #define SSC_TFMR_FSEDGE_OFFSET 24
105 #define SSC_TFMR_FSLEN_SIZE 4
106 #define SSC_TFMR_FSLEN_OFFSET 16
107 #define SSC_TFMR_FSOS_SIZE 3
108 #define SSC_TFMR_FSOS_OFFSET 20
109 #define SSC_TFMR_MSBF_SIZE 1
110 #define SSC_TFMR_MSBF_OFFSET 7
111 
112 /* SSC Receive Hold Register */
113 #define SSC_RHR 0x00000020
114 #define SSC_RHR_RDAT_SIZE 32
115 #define SSC_RHR_RDAT_OFFSET 0
116 
117 /* SSC Transmit Hold Register */
118 #define SSC_THR 0x00000024
119 #define SSC_THR_TDAT_SIZE 32
120 #define SSC_THR_TDAT_OFFSET 0
121 
122 /* SSC Receive Sync. Holding Register */
123 #define SSC_RSHR 0x00000030
124 #define SSC_RSHR_RSDAT_SIZE 16
125 #define SSC_RSHR_RSDAT_OFFSET 0
126 
127 /* SSC Transmit Sync. Holding Register */
128 #define SSC_TSHR 0x00000034
129 #define SSC_TSHR_TSDAT_SIZE 16
130 #define SSC_TSHR_RSDAT_OFFSET 0
131 
132 /* SSC Receive Compare 0 Register */
133 #define SSC_RC0R 0x00000038
134 #define SSC_RC0R_CP0_SIZE 16
135 #define SSC_RC0R_CP0_OFFSET 0
136 
137 /* SSC Receive Compare 1 Register */
138 #define SSC_RC1R 0x0000003c
139 #define SSC_RC1R_CP1_SIZE 16
140 #define SSC_RC1R_CP1_OFFSET 0
141 
142 /* SSC Status Register */
143 #define SSC_SR 0x00000040
144 #define SSC_SR_CP0_SIZE 1
145 #define SSC_SR_CP0_OFFSET 8
146 #define SSC_SR_CP1_SIZE 1
147 #define SSC_SR_CP1_OFFSET 9
148 #define SSC_SR_ENDRX_SIZE 1
149 #define SSC_SR_ENDRX_OFFSET 6
150 #define SSC_SR_ENDTX_SIZE 1
151 #define SSC_SR_ENDTX_OFFSET 2
152 #define SSC_SR_OVRUN_SIZE 1
153 #define SSC_SR_OVRUN_OFFSET 5
154 #define SSC_SR_RXBUFF_SIZE 1
155 #define SSC_SR_RXBUFF_OFFSET 7
156 #define SSC_SR_RXEN_SIZE 1
157 #define SSC_SR_RXEN_OFFSET 17
158 #define SSC_SR_RXRDY_SIZE 1
159 #define SSC_SR_RXRDY_OFFSET 4
160 #define SSC_SR_RXSYN_SIZE 1
161 #define SSC_SR_RXSYN_OFFSET 11
162 #define SSC_SR_TXBUFE_SIZE 1
163 #define SSC_SR_TXBUFE_OFFSET 3
164 #define SSC_SR_TXEMPTY_SIZE 1
165 #define SSC_SR_TXEMPTY_OFFSET 1
166 #define SSC_SR_TXEN_SIZE 1
167 #define SSC_SR_TXEN_OFFSET 16
168 #define SSC_SR_TXRDY_SIZE 1
169 #define SSC_SR_TXRDY_OFFSET 0
170 #define SSC_SR_TXSYN_SIZE 1
171 #define SSC_SR_TXSYN_OFFSET 10
172 
173 /* SSC Interrupt Enable Register */
174 #define SSC_IER 0x00000044
175 #define SSC_IER_CP0_SIZE 1
176 #define SSC_IER_CP0_OFFSET 8
177 #define SSC_IER_CP1_SIZE 1
178 #define SSC_IER_CP1_OFFSET 9
179 #define SSC_IER_ENDRX_SIZE 1
180 #define SSC_IER_ENDRX_OFFSET 6
181 #define SSC_IER_ENDTX_SIZE 1
182 #define SSC_IER_ENDTX_OFFSET 2
183 #define SSC_IER_OVRUN_SIZE 1
184 #define SSC_IER_OVRUN_OFFSET 5
185 #define SSC_IER_RXBUFF_SIZE 1
186 #define SSC_IER_RXBUFF_OFFSET 7
187 #define SSC_IER_RXRDY_SIZE 1
188 #define SSC_IER_RXRDY_OFFSET 4
189 #define SSC_IER_RXSYN_SIZE 1
190 #define SSC_IER_RXSYN_OFFSET 11
191 #define SSC_IER_TXBUFE_SIZE 1
192 #define SSC_IER_TXBUFE_OFFSET 3
193 #define SSC_IER_TXEMPTY_SIZE 1
194 #define SSC_IER_TXEMPTY_OFFSET 1
195 #define SSC_IER_TXRDY_SIZE 1
196 #define SSC_IER_TXRDY_OFFSET 0
197 #define SSC_IER_TXSYN_SIZE 1
198 #define SSC_IER_TXSYN_OFFSET 10
199 
200 /* SSC Interrupt Disable Register */
201 #define SSC_IDR 0x00000048
202 #define SSC_IDR_CP0_SIZE 1
203 #define SSC_IDR_CP0_OFFSET 8
204 #define SSC_IDR_CP1_SIZE 1
205 #define SSC_IDR_CP1_OFFSET 9
206 #define SSC_IDR_ENDRX_SIZE 1
207 #define SSC_IDR_ENDRX_OFFSET 6
208 #define SSC_IDR_ENDTX_SIZE 1
209 #define SSC_IDR_ENDTX_OFFSET 2
210 #define SSC_IDR_OVRUN_SIZE 1
211 #define SSC_IDR_OVRUN_OFFSET 5
212 #define SSC_IDR_RXBUFF_SIZE 1
213 #define SSC_IDR_RXBUFF_OFFSET 7
214 #define SSC_IDR_RXRDY_SIZE 1
215 #define SSC_IDR_RXRDY_OFFSET 4
216 #define SSC_IDR_RXSYN_SIZE 1
217 #define SSC_IDR_RXSYN_OFFSET 11
218 #define SSC_IDR_TXBUFE_SIZE 1
219 #define SSC_IDR_TXBUFE_OFFSET 3
220 #define SSC_IDR_TXEMPTY_SIZE 1
221 #define SSC_IDR_TXEMPTY_OFFSET 1
222 #define SSC_IDR_TXRDY_SIZE 1
223 #define SSC_IDR_TXRDY_OFFSET 0
224 #define SSC_IDR_TXSYN_SIZE 1
225 #define SSC_IDR_TXSYN_OFFSET 10
226 
227 /* SSC Interrupt Mask Register */
228 #define SSC_IMR 0x0000004c
229 #define SSC_IMR_CP0_SIZE 1
230 #define SSC_IMR_CP0_OFFSET 8
231 #define SSC_IMR_CP1_SIZE 1
232 #define SSC_IMR_CP1_OFFSET 9
233 #define SSC_IMR_ENDRX_SIZE 1
234 #define SSC_IMR_ENDRX_OFFSET 6
235 #define SSC_IMR_ENDTX_SIZE 1
236 #define SSC_IMR_ENDTX_OFFSET 2
237 #define SSC_IMR_OVRUN_SIZE 1
238 #define SSC_IMR_OVRUN_OFFSET 5
239 #define SSC_IMR_RXBUFF_SIZE 1
240 #define SSC_IMR_RXBUFF_OFFSET 7
241 #define SSC_IMR_RXRDY_SIZE 1
242 #define SSC_IMR_RXRDY_OFFSET 4
243 #define SSC_IMR_RXSYN_SIZE 1
244 #define SSC_IMR_RXSYN_OFFSET 11
245 #define SSC_IMR_TXBUFE_SIZE 1
246 #define SSC_IMR_TXBUFE_OFFSET 3
247 #define SSC_IMR_TXEMPTY_SIZE 1
248 #define SSC_IMR_TXEMPTY_OFFSET 1
249 #define SSC_IMR_TXRDY_SIZE 1
250 #define SSC_IMR_TXRDY_OFFSET 0
251 #define SSC_IMR_TXSYN_SIZE 1
252 #define SSC_IMR_TXSYN_OFFSET 10
253 
254 /* SSC PDC Receive Pointer Register */
255 #define SSC_PDC_RPR 0x00000100
256 
257 /* SSC PDC Receive Counter Register */
258 #define SSC_PDC_RCR 0x00000104
259 
260 /* SSC PDC Transmit Pointer Register */
261 #define SSC_PDC_TPR 0x00000108
262 
263 /* SSC PDC Receive Next Pointer Register */
264 #define SSC_PDC_RNPR 0x00000110
265 
266 /* SSC PDC Receive Next Counter Register */
267 #define SSC_PDC_RNCR 0x00000114
268 
269 /* SSC PDC Transmit Counter Register */
270 #define SSC_PDC_TCR 0x0000010c
271 
272 /* SSC PDC Transmit Next Pointer Register */
273 #define SSC_PDC_TNPR 0x00000118
274 
275 /* SSC PDC Transmit Next Counter Register */
276 #define SSC_PDC_TNCR 0x0000011c
277 
278 /* SSC PDC Transfer Control Register */
279 #define SSC_PDC_PTCR 0x00000120
280 #define SSC_PDC_PTCR_RXTDIS_SIZE 1
281 #define SSC_PDC_PTCR_RXTDIS_OFFSET 1
282 #define SSC_PDC_PTCR_RXTEN_SIZE 1
283 #define SSC_PDC_PTCR_RXTEN_OFFSET 0
284 #define SSC_PDC_PTCR_TXTDIS_SIZE 1
285 #define SSC_PDC_PTCR_TXTDIS_OFFSET 9
286 #define SSC_PDC_PTCR_TXTEN_SIZE 1
287 #define SSC_PDC_PTCR_TXTEN_OFFSET 8
288 
289 /* SSC PDC Transfer Status Register */
290 #define SSC_PDC_PTSR 0x00000124
291 #define SSC_PDC_PTSR_RXTEN_SIZE 1
292 #define SSC_PDC_PTSR_RXTEN_OFFSET 0
293 #define SSC_PDC_PTSR_TXTEN_SIZE 1
294 #define SSC_PDC_PTSR_TXTEN_OFFSET 8
295 
296 /* Bit manipulation macros */
297 #define SSC_BIT(name) \
298  (1 << SSC_##name##_OFFSET)
299 #define SSC_BF(name, value) \
300  (((value) & ((1 << SSC_##name##_SIZE) - 1)) \
301  << SSC_##name##_OFFSET)
302 #define SSC_BFEXT(name, value) \
303  (((value) >> SSC_##name##_OFFSET) \
304  & ((1 << SSC_##name##_SIZE) - 1))
305 #define SSC_BFINS(name, value, old) \
306  (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \
307  << SSC_##name##_OFFSET)) | SSC_BF(name, value))
308 
309 /* Register access macros */
310 #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
311 #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
312 
313 #endif /* __INCLUDE_ATMEL_SSC_H */