Go to the documentation of this file.
34 #ifndef _BCM1480_INT_H
35 #define _BCM1480_INT_H
63 #define K_BCM1480_INT_SOURCES 128
65 #define _BCM1480_INT_HIGH(k) (k)
66 #define _BCM1480_INT_LOW(k) ((k)+64)
68 #define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1)
69 #define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4)
70 #define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5)
71 #define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6)
72 #define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7)
73 #define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8)
74 #define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9)
75 #define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10)
76 #define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11)
77 #define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12)
78 #define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13)
79 #define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14)
80 #define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15)
81 #define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20)
82 #define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21)
83 #define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22)
84 #define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23)
85 #define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28)
86 #define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29)
87 #define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30)
88 #define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31)
89 #define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36)
90 #define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37)
91 #define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38)
92 #define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39)
93 #define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40)
94 #define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41)
95 #define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42)
96 #define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43)
97 #define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52)
98 #define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53)
99 #define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54)
100 #define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55)
101 #define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56)
102 #define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57)
103 #define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58)
104 #define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59)
105 #define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60)
106 #define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61)
107 #define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62)
108 #define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63)
110 #define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1)
111 #define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2)
112 #define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3)
113 #define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4)
114 #define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5)
115 #define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6)
116 #define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7)
117 #define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8)
118 #define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9)
119 #define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10)
120 #define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11)
121 #define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16)
122 #define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17)
123 #define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18)
124 #define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19)
125 #define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20)
126 #define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21)
127 #define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22)
128 #define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23)
129 #define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24)
130 #define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25)
131 #define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32)
132 #define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33)
133 #define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34)
134 #define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35)
135 #define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36)
136 #define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40)
137 #define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41)
138 #define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42)
139 #define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44)
140 #define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45)
141 #define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46)
142 #define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47)
143 #define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52)
144 #define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53)
145 #define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54)
146 #define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55)
147 #define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56)
148 #define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57)
149 #define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58)
150 #define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59)
151 #define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60)
152 #define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61)
153 #define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62)
154 #define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63)
160 #define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F))
161 #define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
162 #define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
164 #define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
166 #define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
167 #define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
168 #define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
169 #define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
170 #define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
171 #define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
172 #define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
173 #define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
174 #define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
175 #define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
176 #define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
177 #define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
178 #define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
179 #define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
180 #define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
181 #define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
182 #define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
183 #define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
184 #define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
185 #define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
186 #define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
187 #define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
188 #define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
189 #define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
190 #define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
191 #define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
192 #define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
193 #define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
194 #define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
195 #define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
196 #define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
197 #define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
198 #define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
199 #define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
200 #define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
201 #define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
202 #define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
203 #define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
204 #define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
205 #define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
206 #define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
207 #define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
208 #define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
209 #define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
210 #define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
211 #define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
212 #define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
213 #define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
214 #define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
215 #define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
216 #define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
217 #define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
218 #define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
219 #define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
220 #define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
221 #define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
222 #define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
223 #define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
224 #define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
225 #define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
226 #define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
227 #define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
228 #define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
229 #define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
230 #define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
231 #define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
232 #define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
233 #define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
234 #define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
235 #define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
236 #define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
237 #define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
238 #define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
239 #define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
240 #define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
241 #define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
242 #define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
243 #define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
244 #define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
245 #define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
246 #define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
247 #define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
248 #define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
249 #define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
250 #define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
251 #define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
252 #define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
258 #define K_BCM1480_INT_MAP_I0 0
259 #define K_BCM1480_INT_MAP_I1 1
260 #define K_BCM1480_INT_MAP_I2 2
261 #define K_BCM1480_INT_MAP_I3 3
262 #define K_BCM1480_INT_MAP_I4 4
263 #define K_BCM1480_INT_MAP_I5 5
264 #define K_BCM1480_INT_MAP_NMI 6
265 #define K_BCM1480_INT_MAP_DINT 7
271 #define S_BCM1480_INT_HT_INTMSG 0
272 #define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
273 #define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
274 #define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
276 #define K_BCM1480_INT_HT_INTMSG_FIXED 0
277 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1
278 #define K_BCM1480_INT_HT_INTMSG_SMI 2
279 #define K_BCM1480_INT_HT_INTMSG_NMI 3
280 #define K_BCM1480_INT_HT_INTMSG_INIT 4
281 #define K_BCM1480_INT_HT_INTMSG_STARTUP 5
282 #define K_BCM1480_INT_HT_INTMSG_EXTINT 6
283 #define K_BCM1480_INT_HT_INTMSG_RESERVED 7
285 #define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3)
286 #define V_BCM1480_INT_HT_EDGETRIGGER 0
287 #define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE
289 #define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4)
290 #define V_BCM1480_INT_HT_PHYSICALDEST 0
291 #define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE
293 #define S_BCM1480_INT_HT_INTDEST 5
294 #define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
295 #define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
296 #define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
298 #define S_BCM1480_INT_HT_VECTOR 13
299 #define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
300 #define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
301 #define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
307 #define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00
308 #define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40
309 #define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80
310 #define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0