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bf527.h
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1 /*
2  * Copyright 2007-2009 Analog Devices Inc.
3  *
4  * Licensed under the GPL-2 or later.
5  */
6 
7 #ifndef __MACH_BF527_H__
8 #define __MACH_BF527_H__
9 
10 #define OFFSET_(x) ((x) & 0x0000FFFF)
11 
12 /*some misc defines*/
13 #define IMASK_IVG15 0x8000
14 #define IMASK_IVG14 0x4000
15 #define IMASK_IVG13 0x2000
16 #define IMASK_IVG12 0x1000
17 
18 #define IMASK_IVG11 0x0800
19 #define IMASK_IVG10 0x0400
20 #define IMASK_IVG9 0x0200
21 #define IMASK_IVG8 0x0100
22 
23 #define IMASK_IVG7 0x0080
24 #define IMASK_IVGTMR 0x0040
25 #define IMASK_IVGHW 0x0020
26 
27 /***************************/
28 
29 #define BFIN_DSUBBANKS 4
30 #define BFIN_DWAYS 2
31 #define BFIN_DLINES 64
32 #define BFIN_ISUBBANKS 4
33 #define BFIN_IWAYS 4
34 #define BFIN_ILINES 32
35 
36 #define WAY0_L 0x1
37 #define WAY1_L 0x2
38 #define WAY01_L 0x3
39 #define WAY2_L 0x4
40 #define WAY02_L 0x5
41 #define WAY12_L 0x6
42 #define WAY012_L 0x7
43 
44 #define WAY3_L 0x8
45 #define WAY03_L 0x9
46 #define WAY13_L 0xA
47 #define WAY013_L 0xB
48 
49 #define WAY32_L 0xC
50 #define WAY320_L 0xD
51 #define WAY321_L 0xE
52 #define WAYALL_L 0xF
53 
54 #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
55 
56 /********************************* EBIU Settings ************************************/
57 #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
58 #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
59 
60 #ifdef CONFIG_C_AMBEN_ALL
61 #define V_AMBEN AMBEN_ALL
62 #endif
63 #ifdef CONFIG_C_AMBEN
64 #define V_AMBEN 0x0
65 #endif
66 #ifdef CONFIG_C_AMBEN_B0
67 #define V_AMBEN AMBEN_B0
68 #endif
69 #ifdef CONFIG_C_AMBEN_B0_B1
70 #define V_AMBEN AMBEN_B0_B1
71 #endif
72 #ifdef CONFIG_C_AMBEN_B0_B1_B2
73 #define V_AMBEN AMBEN_B0_B1_B2
74 #endif
75 #ifdef CONFIG_C_AMCKEN
76 #define V_AMCKEN AMCKEN
77 #else
78 #define V_AMCKEN 0x0
79 #endif
80 #ifdef CONFIG_C_CDPRIO
81 #define V_CDPRIO 0x100
82 #else
83 #define V_CDPRIO 0x0
84 #endif
85 
86 #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
87 
88 /**************************** Hysteresis Settings ****************************/
89 
90 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
91 #ifdef CONFIG_GPIO_HYST_PORTF_0_7
92 #define HYST_PORTF_0_7 (1 << 0)
93 #else
94 #define HYST_PORTF_0_7 (0 << 0)
95 #endif
96 #ifdef CONFIG_GPIO_HYST_PORTF_8_9
97 #define HYST_PORTF_8_9 (1 << 2)
98 #else
99 #define HYST_PORTF_8_9 (0 << 2)
100 #endif
101 #ifdef CONFIG_GPIO_HYST_PORTF_10
102 #define HYST_PORTF_10 (1 << 4)
103 #else
104 #define HYST_PORTF_10 (0 << 4)
105 #endif
106 #ifdef CONFIG_GPIO_HYST_PORTF_11
107 #define HYST_PORTF_11 (1 << 6)
108 #else
109 #define HYST_PORTF_11 (0 << 6)
110 #endif
111 #ifdef CONFIG_GPIO_HYST_PORTF_12_13
112 #define HYST_PORTF_12_13 (1 << 8)
113 #else
114 #define HYST_PORTF_12_13 (0 << 8)
115 #endif
116 #ifdef CONFIG_GPIO_HYST_PORTF_14_15
117 #define HYST_PORTF_14_15 (1 << 10)
118 #else
119 #define HYST_PORTF_14_15 (0 << 10)
120 #endif
121 
122 #define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
123  HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
124 
125 #ifdef CONFIG_GPIO_HYST_PORTG_0
126 #define HYST_PORTG_0 (1 << 0)
127 #else
128 #define HYST_PORTG_0 (0 << 0)
129 #endif
130 #ifdef CONFIG_GPIO_HYST_PORTG_1_4
131 #define HYST_PORTG_1_4 (1 << 2)
132 #else
133 #define HYST_PORTG_1_4 (0 << 2)
134 #endif
135 #ifdef CONFIG_GPIO_HYST_PORTG_5_6
136 #define HYST_PORTG_5_6 (1 << 4)
137 #else
138 #define HYST_PORTG_5_6 (0 << 4)
139 #endif
140 #ifdef CONFIG_GPIO_HYST_PORTG_7_8
141 #define HYST_PORTG_7_8 (1 << 6)
142 #else
143 #define HYST_PORTG_7_8 (0 << 6)
144 #endif
145 #ifdef CONFIG_GPIO_HYST_PORTG_9
146 #define HYST_PORTG_9 (1 << 8)
147 #else
148 #define HYST_PORTG_9 (0 << 8)
149 #endif
150 #ifdef CONFIG_GPIO_HYST_PORTG_10
151 #define HYST_PORTG_10 (1 << 10)
152 #else
153 #define HYST_PORTG_10 (0 << 10)
154 #endif
155 #ifdef CONFIG_GPIO_HYST_PORTG_11_13
156 #define HYST_PORTG_11_13 (1 << 12)
157 #else
158 #define HYST_PORTG_11_13 (0 << 12)
159 #endif
160 #ifdef CONFIG_GPIO_HYST_PORTG_14_15
161 #define HYST_PORTG_14_15 (1 << 14)
162 #else
163 #define HYST_PORTG_14_15 (0 << 14)
164 #endif
165 
166 #define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
167  HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
168  HYST_PORTG_11_13 | HYST_PORTG_14_15)
169 
170 #ifdef CONFIG_GPIO_HYST_PORTH_0_7
171 #define HYST_PORTH_0_7 (1 << 0)
172 #else
173 #define HYST_PORTH_0_7 (0 << 0)
174 #endif
175 #ifdef CONFIG_GPIO_HYST_PORTH_8
176 #define HYST_PORTH_8 (1 << 2)
177 #else
178 #define HYST_PORTH_8 (0 << 2)
179 #endif
180 #ifdef CONFIG_GPIO_HYST_PORTH_9_15
181 #define HYST_PORTH_9_15 (1 << 4)
182 #else
183 #define HYST_PORTH_9_15 (0 << 4)
184 #endif
185 
186 #define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
187 
188 #ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
189 #define HYST_TMR0_FS1_PPICLK (1 << 0)
190 #else
191 #define HYST_TMR0_FS1_PPICLK (0 << 0)
192 #endif
193 #ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
194 #define HYST_NMI_RST_BMODE (1 << 2)
195 #else
196 #define HYST_NMI_RST_BMODE (0 << 2)
197 #endif
198 #ifdef CONFIG_NONEGPIO_HYST_JTAG
199 #define HYST_JTAG (1 << 4)
200 #else
201 #define HYST_JTAG (0 << 4)
202 #endif
203 
204 #define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
205 #define HYST_NONEGPIO_MASK (0x3F)
206 #endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
207 
208 #ifdef CONFIG_BF527
209 #define CPU "BF527"
210 #define CPUID 0x27e0
211 #endif
212 #ifdef CONFIG_BF526
213 #define CPU "BF526"
214 #define CPUID 0x27e4
215 #endif
216 #ifdef CONFIG_BF525
217 #define CPU "BF525"
218 #define CPUID 0x27e0
219 #endif
220 #ifdef CONFIG_BF524
221 #define CPU "BF524"
222 #define CPUID 0x27e4
223 #endif
224 #ifdef CONFIG_BF523
225 #define CPU "BF523"
226 #define CPUID 0x27e0
227 #endif
228 #ifdef CONFIG_BF522
229 #define CPU "BF522"
230 #define CPUID 0x27e4
231 #endif
232 
233 #ifndef CPU
234 #error "Unknown CPU type - This kernel doesn't seem to be configured properly"
235 #endif
236 
237 #endif /* __MACH_BF527_H__ */