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bf561.h
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1 /*
2  * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
3  *
4  * Copyright 2005-2008 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2 or later.
7  */
8 
9 #ifndef __MACH_BF561_H__
10 #define __MACH_BF561_H__
11 
12 #define OFFSET_(x) ((x) & 0x0000FFFF)
13 
14 /*some misc defines*/
15 #define IMASK_IVG15 0x8000
16 #define IMASK_IVG14 0x4000
17 #define IMASK_IVG13 0x2000
18 #define IMASK_IVG12 0x1000
19 
20 #define IMASK_IVG11 0x0800
21 #define IMASK_IVG10 0x0400
22 #define IMASK_IVG9 0x0200
23 #define IMASK_IVG8 0x0100
24 
25 #define IMASK_IVG7 0x0080
26 #define IMASK_IVGTMR 0x0040
27 #define IMASK_IVGHW 0x0020
28 
29 /***************************
30  * Blackfin Cache setup
31  */
32 
33 
34 #define BFIN_ISUBBANKS 4
35 #define BFIN_IWAYS 4
36 #define BFIN_ILINES 32
37 
38 #define BFIN_DSUBBANKS 4
39 #define BFIN_DWAYS 2
40 #define BFIN_DLINES 64
41 
42 #define WAY0_L 0x1
43 #define WAY1_L 0x2
44 #define WAY01_L 0x3
45 #define WAY2_L 0x4
46 #define WAY02_L 0x5
47 #define WAY12_L 0x6
48 #define WAY012_L 0x7
49 
50 #define WAY3_L 0x8
51 #define WAY03_L 0x9
52 #define WAY13_L 0xA
53 #define WAY013_L 0xB
54 
55 #define WAY32_L 0xC
56 #define WAY320_L 0xD
57 #define WAY321_L 0xE
58 #define WAYALL_L 0xF
59 
60 #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
61 
62 /* IAR0 BIT FIELDS */
63 #define PLL_WAKEUP_BIT 0xFFFFFFFF
64 #define DMA1_ERROR_BIT 0xFFFFFF0F
65 #define DMA2_ERROR_BIT 0xFFFFF0FF
66 #define IMDMA_ERROR_BIT 0xFFFF0FFF
67 #define PPI1_ERROR_BIT 0xFFF0FFFF
68 #define PPI2_ERROR_BIT 0xFF0FFFFF
69 #define SPORT0_ERROR_BIT 0xF0FFFFFF
70 #define SPORT1_ERROR_BIT 0x0FFFFFFF
71 /* IAR1 BIT FIELDS */
72 #define SPI_ERROR_BIT 0xFFFFFFFF
73 #define UART_ERROR_BIT 0xFFFFFF0F
74 #define RESERVED_ERROR_BIT 0xFFFFF0FF
75 #define DMA1_0_BIT 0xFFFF0FFF
76 #define DMA1_1_BIT 0xFFF0FFFF
77 #define DMA1_2_BIT 0xFF0FFFFF
78 #define DMA1_3_BIT 0xF0FFFFFF
79 #define DMA1_4_BIT 0x0FFFFFFF
80 /* IAR2 BIT FIELDS */
81 #define DMA1_5_BIT 0xFFFFFFFF
82 #define DMA1_6_BIT 0xFFFFFF0F
83 #define DMA1_7_BIT 0xFFFFF0FF
84 #define DMA1_8_BIT 0xFFFF0FFF
85 #define DMA1_9_BIT 0xFFF0FFFF
86 #define DMA1_10_BIT 0xFF0FFFFF
87 #define DMA1_11_BIT 0xF0FFFFFF
88 #define DMA2_0_BIT 0x0FFFFFFF
89 /* IAR3 BIT FIELDS */
90 #define DMA2_1_BIT 0xFFFFFFFF
91 #define DMA2_2_BIT 0xFFFFFF0F
92 #define DMA2_3_BIT 0xFFFFF0FF
93 #define DMA2_4_BIT 0xFFFF0FFF
94 #define DMA2_5_BIT 0xFFF0FFFF
95 #define DMA2_6_BIT 0xFF0FFFFF
96 #define DMA2_7_BIT 0xF0FFFFFF
97 #define DMA2_8_BIT 0x0FFFFFFF
98 /* IAR4 BIT FIELDS */
99 #define DMA2_9_BIT 0xFFFFFFFF
100 #define DMA2_10_BIT 0xFFFFFF0F
101 #define DMA2_11_BIT 0xFFFFF0FF
102 #define TIMER0_BIT 0xFFFF0FFF
103 #define TIMER1_BIT 0xFFF0FFFF
104 #define TIMER2_BIT 0xFF0FFFFF
105 #define TIMER3_BIT 0xF0FFFFFF
106 #define TIMER4_BIT 0x0FFFFFFF
107 /* IAR5 BIT FIELDS */
108 #define TIMER5_BIT 0xFFFFFFFF
109 #define TIMER6_BIT 0xFFFFFF0F
110 #define TIMER7_BIT 0xFFFFF0FF
111 #define TIMER8_BIT 0xFFFF0FFF
112 #define TIMER9_BIT 0xFFF0FFFF
113 #define TIMER10_BIT 0xFF0FFFFF
114 #define TIMER11_BIT 0xF0FFFFFF
115 #define PROG0_INTA_BIT 0x0FFFFFFF
116 /* IAR6 BIT FIELDS */
117 #define PROG0_INTB_BIT 0xFFFFFFFF
118 #define PROG1_INTA_BIT 0xFFFFFF0F
119 #define PROG1_INTB_BIT 0xFFFFF0FF
120 #define PROG2_INTA_BIT 0xFFFF0FFF
121 #define PROG2_INTB_BIT 0xFFF0FFFF
122 #define DMA1_WRRD0_BIT 0xFF0FFFFF
123 #define DMA1_WRRD1_BIT 0xF0FFFFFF
124 #define DMA2_WRRD0_BIT 0x0FFFFFFF
125 /* IAR7 BIT FIELDS */
126 #define DMA2_WRRD1_BIT 0xFFFFFFFF
127 #define IMDMA_WRRD0_BIT 0xFFFFFF0F
128 #define IMDMA_WRRD1_BIT 0xFFFFF0FF
129 #define WATCH_BIT 0xFFFF0FFF
130 #define RESERVED_1_BIT 0xFFF0FFFF
131 #define RESERVED_2_BIT 0xFF0FFFFF
132 #define SUPPLE_0_BIT 0xF0FFFFFF
133 #define SUPPLE_1_BIT 0x0FFFFFFF
134 
135 /* Miscellaneous Values */
136 
137 /****************************** EBIU Settings ********************************/
138 #define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
139 #define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
140 
141 #if defined(CONFIG_C_AMBEN_ALL)
142 #define V_AMBEN AMBEN_ALL
143 #elif defined(CONFIG_C_AMBEN)
144 #define V_AMBEN 0x0
145 #elif defined(CONFIG_C_AMBEN_B0)
146 #define V_AMBEN AMBEN_B0
147 #elif defined(CONFIG_C_AMBEN_B0_B1)
148 #define V_AMBEN AMBEN_B0_B1
149 #elif defined(CONFIG_C_AMBEN_B0_B1_B2)
150 #define V_AMBEN AMBEN_B0_B1_B2
151 #endif
152 
153 #ifdef CONFIG_C_AMCKEN
154 #define V_AMCKEN AMCKEN
155 #else
156 #define V_AMCKEN 0x0
157 #endif
158 
159 #ifdef CONFIG_C_B0PEN
160 #define V_B0PEN 0x10
161 #else
162 #define V_B0PEN 0x00
163 #endif
164 
165 #ifdef CONFIG_C_B1PEN
166 #define V_B1PEN 0x20
167 #else
168 #define V_B1PEN 0x00
169 #endif
170 
171 #ifdef CONFIG_C_B2PEN
172 #define V_B2PEN 0x40
173 #else
174 #define V_B2PEN 0x00
175 #endif
176 
177 #ifdef CONFIG_C_B3PEN
178 #define V_B3PEN 0x80
179 #else
180 #define V_B3PEN 0x00
181 #endif
182 
183 #ifdef CONFIG_C_CDPRIO
184 #define V_CDPRIO 0x100
185 #else
186 #define V_CDPRIO 0x0
187 #endif
188 
189 #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
190 
191 #ifdef CONFIG_BF561
192 #define CPU "BF561"
193 #define CPUID 0x27bb
194 #endif
195 
196 #ifndef CPU
197 #error "Unknown CPU type - This kernel doesn't seem to be configured properly"
198 #endif
199 
200 #endif /* __MACH_BF561_H__ */