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17 #define BP_CAP 0x01 //BIT_0
18 #define BP_STATUS_CAP 0x02 //BIT_1
19 #define BP_STATUS_CHANGE_CAP 0x04 //BIT_2
20 #define SW_CTL_CAP 0x08 //BIT_3
21 #define BP_DIS_CAP 0x10 //BIT_4
22 #define BP_DIS_STATUS_CAP 0x20 //BIT_5
23 #define STD_NIC_CAP 0x40 //BIT_6
24 #define BP_PWOFF_ON_CAP 0x80 //BIT_7
25 #define BP_PWOFF_OFF_CAP 0x0100 //BIT_8
26 #define BP_PWOFF_CTL_CAP 0x0200 //BIT_9
27 #define BP_PWUP_ON_CAP 0x0400 //BIT_10
28 #define BP_PWUP_OFF_CAP 0x0800 //BIT_11
29 #define BP_PWUP_CTL_CAP 0x1000 //BIT_12
30 #define WD_CTL_CAP 0x2000 //BIT_13
31 #define WD_STATUS_CAP 0x4000 //BIT_14
32 #define WD_TIMEOUT_CAP 0x8000 //BIT_15
33 #define TX_CTL_CAP 0x10000 //BIT_16
34 #define TX_STATUS_CAP 0x20000 //BIT_17
35 #define TAP_CAP 0x40000 //BIT_18
36 #define TAP_STATUS_CAP 0x80000 //BIT_19
37 #define TAP_STATUS_CHANGE_CAP 0x100000 //BIT_20
38 #define TAP_DIS_CAP 0x200000 //BIT_21
39 #define TAP_DIS_STATUS_CAP 0x400000 //BIT_22
40 #define TAP_PWUP_ON_CAP 0x800000 //BIT_23
41 #define TAP_PWUP_OFF_CAP 0x1000000 //BIT 24
42 #define TAP_PWUP_CTL_CAP 0x2000000 //BIT 25
43 #define NIC_CAP_NEG 0x4000000 //BIT 26
44 #define TPL_CAP 0x8000000 //BIT 27
45 #define DISC_CAP 0x10000000 //BIT 28
46 #define DISC_DIS_CAP 0x20000000 //BIT 29
47 #define DISC_PWUP_CTL_CAP 0x40000000 //BIT 30
49 #define WD_MIN_TIME_MASK(val) (val & 0xf)
50 #define WD_STEP_COUNT_MASK(val) ((val & 0xf) << 5)
51 #define WDT_STEP_TIME 0x10 //BIT_4
53 #define WD_MIN_TIME_GET(desc) (desc & 0xf)
54 #define WD_STEP_COUNT_GET(desc) (desc>>5) & 0xf
159 #define SIOCGIFBYPASS SIOCDEVPRIVATE+10
184 #define MAGIC_NUM 'J'
194 #define IOCTL_TX_MSG(cmd) _IOWR(MAGIC_NUM, cmd, struct bpctl_cmd)
196 #define DEVICE_NAME "bpctl"