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class.h
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1 #ifndef __NOUVEAU_CLASS_H__
2 #define __NOUVEAU_CLASS_H__
3 
4 /* Device class
5  *
6  * 0080: NV_DEVICE
7  */
8 #define NV_DEVICE_CLASS 0x00000080
9 
10 #define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL
11 #define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL
12 #define NV_DEVICE_DISABLE_VBIOS 0x0000000000000004ULL
13 #define NV_DEVICE_DISABLE_CORE 0x0000000000000008ULL
14 #define NV_DEVICE_DISABLE_DISP 0x0000000000010000ULL
15 #define NV_DEVICE_DISABLE_FIFO 0x0000000000020000ULL
16 #define NV_DEVICE_DISABLE_GRAPH 0x0000000100000000ULL
17 #define NV_DEVICE_DISABLE_MPEG 0x0000000200000000ULL
18 #define NV_DEVICE_DISABLE_ME 0x0000000400000000ULL
19 #define NV_DEVICE_DISABLE_VP 0x0000000800000000ULL
20 #define NV_DEVICE_DISABLE_CRYPT 0x0000001000000000ULL
21 #define NV_DEVICE_DISABLE_BSP 0x0000002000000000ULL
22 #define NV_DEVICE_DISABLE_PPP 0x0000004000000000ULL
23 #define NV_DEVICE_DISABLE_COPY0 0x0000008000000000ULL
24 #define NV_DEVICE_DISABLE_COPY1 0x0000010000000000ULL
25 #define NV_DEVICE_DISABLE_UNK1C1 0x0000020000000000ULL
26 
28  u64 device; /* device identifier, ~0 for client default */
29  u64 disable; /* disable particular subsystems */
30  u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
31 };
32 
33 /* DMA object classes
34  *
35  * 0002: NV_DMA_FROM_MEMORY
36  * 0003: NV_DMA_TO_MEMORY
37  * 003d: NV_DMA_IN_MEMORY
38  */
39 #define NV_DMA_FROM_MEMORY_CLASS 0x00000002
40 #define NV_DMA_TO_MEMORY_CLASS 0x00000003
41 #define NV_DMA_IN_MEMORY_CLASS 0x0000003d
42 
43 #define NV_DMA_TARGET_MASK 0x000000ff
44 #define NV_DMA_TARGET_VM 0x00000000
45 #define NV_DMA_TARGET_VRAM 0x00000001
46 #define NV_DMA_TARGET_PCI 0x00000002
47 #define NV_DMA_TARGET_PCI_US 0x00000003
48 #define NV_DMA_TARGET_AGP 0x00000004
49 #define NV_DMA_ACCESS_MASK 0x00000f00
50 #define NV_DMA_ACCESS_VM 0x00000000
51 #define NV_DMA_ACCESS_RD 0x00000100
52 #define NV_DMA_ACCESS_WR 0x00000200
53 #define NV_DMA_ACCESS_RDWR 0x00000300
54 
55 struct nv_dma_class {
60 };
61 
62 /* DMA FIFO channel classes
63  *
64  * 006b: NV03_CHANNEL_DMA
65  * 006e: NV10_CHANNEL_DMA
66  * 176e: NV17_CHANNEL_DMA
67  * 406e: NV40_CHANNEL_DMA
68  * 506e: NV50_CHANNEL_DMA
69  * 826e: NV84_CHANNEL_DMA
70  */
71 #define NV03_CHANNEL_DMA_CLASS 0x0000006b
72 #define NV10_CHANNEL_DMA_CLASS 0x0000006e
73 #define NV17_CHANNEL_DMA_CLASS 0x0000176e
74 #define NV40_CHANNEL_DMA_CLASS 0x0000406e
75 #define NV50_CHANNEL_DMA_CLASS 0x0000506e
76 #define NV84_CHANNEL_DMA_CLASS 0x0000826e
77 
82 };
83 
84 /* Indirect FIFO channel classes
85  *
86  * 506f: NV50_CHANNEL_IND
87  * 826f: NV84_CHANNEL_IND
88  * 906f: NVC0_CHANNEL_IND
89  * a06f: NVE0_CHANNEL_IND
90  */
91 
92 #define NV50_CHANNEL_IND_CLASS 0x0000506f
93 #define NV84_CHANNEL_IND_CLASS 0x0000826f
94 #define NVC0_CHANNEL_IND_CLASS 0x0000906f
95 #define NVE0_CHANNEL_IND_CLASS 0x0000a06f
96 
101 };
102 
103 #define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001
104 #define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002
105 #define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004
106 #define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008
107 #define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010
108 #define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020
109 #define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040
110 
116 };
117 
118 #endif