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clk-imx31.c
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1 /*
2  * Copyright (C) 2012 Sascha Hauer <[email protected]>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation.
16  */
17 
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <linux/clkdev.h>
21 #include <linux/io.h>
22 #include <linux/err.h>
23 #include <linux/of.h>
24 
25 #include <mach/hardware.h>
26 #include <mach/mx31.h>
27 #include <mach/common.h>
28 
29 #include "clk.h"
30 #include "crmregs-imx3.h"
31 
32 static const char *mcu_main_sel[] = { "spll", "mpll", };
33 static const char *per_sel[] = { "per_div", "ipg", };
34 static const char *csi_sel[] = { "upll", "spll", };
35 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
36 
37 enum mx31_clks {
38  ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
39  per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
40  fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
41  iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
42  uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
43  mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
44  sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
45  uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
46  gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
47 };
48 
49 static struct clk *clk[clk_max];
50 
51 int __init mx31_clocks_init(unsigned long fref)
52 {
53  void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
54  int i;
55 
56  clk[ckih] = imx_clk_fixed("ckih", fref);
57  clk[ckil] = imx_clk_fixed("ckil", 32768);
58  clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
59  clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL);
60  clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL);
61  clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
62  clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
63  clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
64  clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
65  clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
66  clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
67  clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
68  clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
69  clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
70  clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
71  clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
72  clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
73  clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
74  clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
75  clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
76  clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
77  clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
78  clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
79  clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
80  clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
81  clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
82  clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
83  clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
84  clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
85  clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
86  clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
87  clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
88  clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
89  clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
90  clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
91  clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
92  clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
93  clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
94  clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
95  clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
96  clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
97  clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
98  clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
99  clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
100  clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
101  clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
102  clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
103  clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
104  clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
105  clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
106  clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
107  clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
108  clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
109  clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
110  clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
111  clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
112  clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
113  clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
114 
115  for (i = 0; i < ARRAY_SIZE(clk); i++)
116  if (IS_ERR(clk[i]))
117  pr_err("imx31 clk %d: register failed with %ld\n",
118  i, PTR_ERR(clk[i]));
119 
120  clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
121  clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
122  clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
123  clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
124  clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
125  clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
126  clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
127  clk_register_clkdev(clk[rtc_gate], NULL, "mxc_rtc");
128  clk_register_clkdev(clk[epit1_gate], "epit", NULL);
129  clk_register_clkdev(clk[epit2_gate], "epit", NULL);
130  clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
131  clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
132  clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
133  clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
134  clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
135  clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
136  clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
137  clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
138  clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
139  clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
140  clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
141  clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
142  clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
143  clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc");
144  clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc");
145  clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
146  clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
147  /* i.mx31 has the i.mx21 type uart */
148  clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
149  clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
150  clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
151  clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
152  clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
153  clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
154  clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
155  clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
156  clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
157  clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
158  clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
159  clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
160  clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
161  clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
162  clk_register_clkdev(clk[sdhc1_gate], NULL, "mxc-mmc.0");
163  clk_register_clkdev(clk[sdhc2_gate], NULL, "mxc-mmc.1");
164  clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
165  clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
166  clk_register_clkdev(clk[firi_gate], "firi", NULL);
167  clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
168  clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
169  clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
170  clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
171  clk_register_clkdev(clk[iim_gate], "iim", NULL);
172 
173  clk_set_parent(clk[csi], clk[upll]);
174  clk_prepare_enable(clk[emi_gate]);
175  clk_prepare_enable(clk[iim_gate]);
176  mx31_revision();
177  clk_disable_unprepare(clk[iim_gate]);
178 
179  mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
180 
181  return 0;
182 }
183 
184 #ifdef CONFIG_OF
185 int __init mx31_clocks_init_dt(void)
186 {
187  struct device_node *np;
188  u32 fref = 26000000; /* default */
189 
190  for_each_compatible_node(np, NULL, "fixed-clock") {
191  if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
192  continue;
193 
194  if (!of_property_read_u32(np, "clock-frequency", &fref))
195  break;
196  }
197 
198  return mx31_clocks_init(fref);
199 }
200 #endif
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