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11 #ifndef __ASM_HARDWARE_CP_INTC_H
12 #define __ASM_HARDWARE_CP_INTC_H
14 #define CP_INTC_REV 0x00
15 #define CP_INTC_CTRL 0x04
16 #define CP_INTC_HOST_CTRL 0x0C
17 #define CP_INTC_GLOBAL_ENABLE 0x10
18 #define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C
19 #define CP_INTC_SYS_STAT_IDX_SET 0x20
20 #define CP_INTC_SYS_STAT_IDX_CLR 0x24
21 #define CP_INTC_SYS_ENABLE_IDX_SET 0x28
22 #define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
23 #define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30
24 #define CP_INTC_HOST_ENABLE_IDX_SET 0x34
25 #define CP_INTC_HOST_ENABLE_IDX_CLR 0x38
26 #define CP_INTC_PACING_PRESCALE 0x40
27 #define CP_INTC_VECTOR_BASE 0x50
28 #define CP_INTC_VECTOR_SIZE 0x54
29 #define CP_INTC_VECTOR_NULL 0x58
30 #define CP_INTC_PRIO_IDX 0x80
31 #define CP_INTC_PRIO_VECTOR 0x84
32 #define CP_INTC_SECURE_ENABLE 0x90
33 #define CP_INTC_SECURE_PRIO_IDX 0x94
34 #define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4))
35 #define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4))
36 #define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4))
37 #define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2))
38 #define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
39 #define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2))
40 #define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
41 #define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
42 #define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2))
43 #define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2))
44 #define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
45 #define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
46 #define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2))
47 #define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2))
48 #define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2))
49 #define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2))
50 #define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
51 #define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2))
52 #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))