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cpufreq-pxa2xx.c
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1 /*
2  * linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c
3  *
4  * Copyright (C) 2002,2003 Intrinsyc Software
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19  *
20  * History:
21  * 31-Jul-2002 : Initial version [FB]
22  * 29-Jan-2003 : added PXA255 support [FB]
23  * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
24  *
25  * Note:
26  * This driver may change the memory bus clock rate, but will not do any
27  * platform specific access timing changes... for example if you have flash
28  * memory connected to CS0, you will need to register a platform specific
29  * notifier which will adjust the memory access strobes to maintain a
30  * minimum strobe width.
31  *
32  */
33 
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/sched.h>
37 #include <linux/init.h>
38 #include <linux/cpufreq.h>
39 #include <linux/err.h>
41 #include <linux/io.h>
42 
43 #include <mach/pxa2xx-regs.h>
44 #include <mach/smemc.h>
45 
46 #ifdef DEBUG
47 static unsigned int freq_debug;
49 MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
50 #else
51 #define freq_debug 0
52 #endif
53 
54 static struct regulator *vcc_core;
55 
56 static unsigned int pxa27x_maxfreq;
57 module_param(pxa27x_maxfreq, uint, 0);
58 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
59  "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
60 
61 typedef struct {
62  unsigned int khz;
63  unsigned int membus;
64  unsigned int cccr;
65  unsigned int div2;
66  unsigned int cclkcfg;
67  int vmin;
68  int vmax;
69 } pxa_freqs_t;
70 
71 /* Define the refresh period in mSec for the SDRAM and the number of rows */
72 #define SDRAM_TREF 64 /* standard 64ms SDRAM */
73 static unsigned int sdram_rows;
74 
75 #define CCLKCFG_TURBO 0x1
76 #define CCLKCFG_FCS 0x2
77 #define CCLKCFG_HALFTURBO 0x4
78 #define CCLKCFG_FASTBUS 0x8
79 #define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
80 #define MDREFR_DRI_MASK 0xFFF
81 
82 #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
83 #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
84 
85 /*
86  * PXA255 definitions
87  */
88 /* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
89 #define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
90 
91 static pxa_freqs_t pxa255_run_freqs[] =
92 {
93  /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
94  { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
95  {132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
96  {199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
97  {265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
98  {331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
99  {398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
100 };
101 
102 /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
103 static pxa_freqs_t pxa255_turbo_freqs[] =
104 {
105  /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
106  { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
107  {199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
108  {298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
109  {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
110  {398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
111 };
112 
113 #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
114 #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
115 
116 static struct cpufreq_frequency_table
117  pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
118 static struct cpufreq_frequency_table
119  pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
120 
121 static unsigned int pxa255_turbo_table;
122 module_param(pxa255_turbo_table, uint, 0);
123 MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
124 
125 /*
126  * PXA270 definitions
127  *
128  * For the PXA27x:
129  * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
130  *
131  * A = 0 => memory controller clock from table 3-7,
132  * A = 1 => memory controller clock = system bus clock
133  * Run mode frequency = 13 MHz * L
134  * Turbo mode frequency = 13 MHz * L * N
135  * System bus frequency = 13 MHz * L / (B + 1)
136  *
137  * In CCCR:
138  * A = 1
139  * L = 16 oscillator to run mode ratio
140  * 2N = 6 2 * (turbo mode to run mode ratio)
141  *
142  * In CCLKCFG:
143  * B = 1 Fast bus mode
144  * HT = 0 Half-Turbo mode
145  * T = 1 Turbo mode
146  *
147  * For now, just support some of the combinations in table 3-7 of
148  * PXA27x Processor Family Developer's Manual to simplify frequency
149  * change sequences.
150  */
151 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
152 #define CCLKCFG2(B, HT, T) \
153  (CCLKCFG_FCS | \
154  ((B) ? CCLKCFG_FASTBUS : 0) | \
155  ((HT) ? CCLKCFG_HALFTURBO : 0) | \
156  ((T) ? CCLKCFG_TURBO : 0))
157 
158 static pxa_freqs_t pxa27x_freqs[] = {
159  {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
160  {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
161  {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
162  {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
163  {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
164  {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
165  {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
166 };
167 
168 #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
169 static struct cpufreq_frequency_table
170  pxa27x_freq_table[NUM_PXA27x_FREQS+1];
171 
172 extern unsigned get_clk_frequency_khz(int info);
173 
174 #ifdef CONFIG_REGULATOR
175 
176 static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
177 {
178  int ret = 0;
179  int vmin, vmax;
180 
181  if (!cpu_is_pxa27x())
182  return 0;
183 
184  vmin = pxa_freq->vmin;
185  vmax = pxa_freq->vmax;
186  if ((vmin == -1) || (vmax == -1))
187  return 0;
188 
189  ret = regulator_set_voltage(vcc_core, vmin, vmax);
190  if (ret)
191  pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
192  vmin, vmax);
193  return ret;
194 }
195 
196 static __init void pxa_cpufreq_init_voltages(void)
197 {
198  vcc_core = regulator_get(NULL, "vcc_core");
199  if (IS_ERR(vcc_core)) {
200  pr_info("cpufreq: Didn't find vcc_core regulator\n");
201  vcc_core = NULL;
202  } else {
203  pr_info("cpufreq: Found vcc_core regulator\n");
204  }
205 }
206 #else
207 static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
208 {
209  return 0;
210 }
211 
212 static __init void pxa_cpufreq_init_voltages(void) { }
213 #endif
214 
215 static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
216  pxa_freqs_t **pxa_freqs)
217 {
218  if (cpu_is_pxa25x()) {
219  if (!pxa255_turbo_table) {
220  *pxa_freqs = pxa255_run_freqs;
221  *freq_table = pxa255_run_freq_table;
222  } else {
223  *pxa_freqs = pxa255_turbo_freqs;
224  *freq_table = pxa255_turbo_freq_table;
225  }
226  }
227  if (cpu_is_pxa27x()) {
228  *pxa_freqs = pxa27x_freqs;
229  *freq_table = pxa27x_freq_table;
230  }
231 }
232 
233 static void pxa27x_guess_max_freq(void)
234 {
235  if (!pxa27x_maxfreq) {
236  pxa27x_maxfreq = 416000;
237  printk(KERN_INFO "PXA CPU 27x max frequency not defined "
238  "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
239  pxa27x_maxfreq);
240  } else {
241  pxa27x_maxfreq *= 1000;
242  }
243 }
244 
245 static void init_sdram_rows(void)
246 {
247  uint32_t mdcnfg = __raw_readl(MDCNFG);
248  unsigned int drac2 = 0, drac0 = 0;
249 
250  if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
251  drac2 = MDCNFG_DRAC2(mdcnfg);
252 
253  if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
254  drac0 = MDCNFG_DRAC0(mdcnfg);
255 
256  sdram_rows = 1 << (11 + max(drac0, drac2));
257 }
258 
259 static u32 mdrefr_dri(unsigned int freq)
260 {
261  u32 interval = freq * SDRAM_TREF / sdram_rows;
262 
263  return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
264 }
265 
266 /* find a valid frequency point */
267 static int pxa_verify_policy(struct cpufreq_policy *policy)
268 {
269  struct cpufreq_frequency_table *pxa_freqs_table;
270  pxa_freqs_t *pxa_freqs;
271  int ret;
272 
273  find_freq_tables(&pxa_freqs_table, &pxa_freqs);
274  ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
275 
276  if (freq_debug)
277  pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
278  policy->min, policy->max);
279 
280  return ret;
281 }
282 
283 static unsigned int pxa_cpufreq_get(unsigned int cpu)
284 {
285  return get_clk_frequency_khz(0);
286 }
287 
288 static int pxa_set_target(struct cpufreq_policy *policy,
289  unsigned int target_freq,
290  unsigned int relation)
291 {
292  struct cpufreq_frequency_table *pxa_freqs_table;
293  pxa_freqs_t *pxa_freq_settings;
294  struct cpufreq_freqs freqs;
295  unsigned int idx;
296  unsigned long flags;
297  unsigned int new_freq_cpu, new_freq_mem;
298  unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
299  int ret = 0;
300 
301  /* Get the current policy */
302  find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
303 
304  /* Lookup the next frequency */
305  if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
306  target_freq, relation, &idx)) {
307  return -EINVAL;
308  }
309 
310  new_freq_cpu = pxa_freq_settings[idx].khz;
311  new_freq_mem = pxa_freq_settings[idx].membus;
312  freqs.old = policy->cur;
313  freqs.new = new_freq_cpu;
314  freqs.cpu = policy->cpu;
315 
316  if (freq_debug)
317  pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
318  freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
319  (new_freq_mem / 2000) : (new_freq_mem / 1000));
320 
321  if (vcc_core && freqs.new > freqs.old)
322  ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
323  if (ret)
324  return ret;
325  /*
326  * Tell everyone what we're about to do...
327  * you should add a notify client with any platform specific
328  * Vcc changing capability
329  */
331 
332  /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
333  * we need to preset the smaller DRI before the change. If we're
334  * speeding up we need to set the larger DRI value after the change.
335  */
336  preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
337  if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
338  preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
339  preset_mdrefr |= mdrefr_dri(new_freq_mem);
340  }
341  postset_mdrefr =
342  (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
343 
344  /* If we're dividing the memory clock by two for the SDRAM clock, this
345  * must be set prior to the change. Clearing the divide must be done
346  * after the change.
347  */
348  if (pxa_freq_settings[idx].div2) {
349  preset_mdrefr |= MDREFR_DB2_MASK;
350  postset_mdrefr |= MDREFR_DB2_MASK;
351  } else {
352  postset_mdrefr &= ~MDREFR_DB2_MASK;
353  }
354 
355  local_irq_save(flags);
356 
357  /* Set new the CCCR and prepare CCLKCFG */
358  CCCR = pxa_freq_settings[idx].cccr;
359  cclkcfg = pxa_freq_settings[idx].cclkcfg;
360 
361  asm volatile(" \n\
362  ldr r4, [%1] /* load MDREFR */ \n\
363  b 2f \n\
364  .align 5 \n\
365 1: \n\
366  str %3, [%1] /* preset the MDREFR */ \n\
367  mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
368  str %4, [%1] /* postset the MDREFR */ \n\
369  \n\
370  b 3f \n\
371 2: b 1b \n\
372 3: nop \n\
373  "
374  : "=&r" (unused)
375  : "r" (MDREFR), "r" (cclkcfg),
376  "r" (preset_mdrefr), "r" (postset_mdrefr)
377  : "r4", "r5");
378  local_irq_restore(flags);
379 
380  /*
381  * Tell everyone what we've just done...
382  * you should add a notify client with any platform specific
383  * SDRAM refresh timer adjustments
384  */
386 
387  /*
388  * Even if voltage setting fails, we don't report it, as the frequency
389  * change succeeded. The voltage reduction is not a critical failure,
390  * only power savings will suffer from this.
391  *
392  * Note: if the voltage change fails, and a return value is returned, a
393  * bug is triggered (seems a deadlock). Should anybody find out where,
394  * the "return 0" should become a "return ret".
395  */
396  if (vcc_core && freqs.new < freqs.old)
397  ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
398 
399  return 0;
400 }
401 
402 static int pxa_cpufreq_init(struct cpufreq_policy *policy)
403 {
404  int i;
405  unsigned int freq;
406  struct cpufreq_frequency_table *pxa255_freq_table;
407  pxa_freqs_t *pxa255_freqs;
408 
409  /* try to guess pxa27x cpu */
410  if (cpu_is_pxa27x())
411  pxa27x_guess_max_freq();
412 
413  pxa_cpufreq_init_voltages();
414 
415  init_sdram_rows();
416 
417  /* set default policy and cpuinfo */
418  policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
419  policy->cur = get_clk_frequency_khz(0); /* current freq */
420  policy->min = policy->max = policy->cur;
421 
422  /* Generate pxa25x the run cpufreq_frequency_table struct */
423  for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
424  pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
425  pxa255_run_freq_table[i].index = i;
426  }
427  pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
428 
429  /* Generate pxa25x the turbo cpufreq_frequency_table struct */
430  for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
431  pxa255_turbo_freq_table[i].frequency =
432  pxa255_turbo_freqs[i].khz;
433  pxa255_turbo_freq_table[i].index = i;
434  }
435  pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
436 
437  pxa255_turbo_table = !!pxa255_turbo_table;
438 
439  /* Generate the pxa27x cpufreq_frequency_table struct */
440  for (i = 0; i < NUM_PXA27x_FREQS; i++) {
441  freq = pxa27x_freqs[i].khz;
442  if (freq > pxa27x_maxfreq)
443  break;
444  pxa27x_freq_table[i].frequency = freq;
445  pxa27x_freq_table[i].index = i;
446  }
447  pxa27x_freq_table[i].index = i;
448  pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
449 
450  /*
451  * Set the policy's minimum and maximum frequencies from the tables
452  * just constructed. This sets cpuinfo.mxx_freq, min and max.
453  */
454  if (cpu_is_pxa25x()) {
455  find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
456  pr_info("PXA255 cpufreq using %s frequency table\n",
457  pxa255_turbo_table ? "turbo" : "run");
458  cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
459  }
460  else if (cpu_is_pxa27x())
461  cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
462 
463  printk(KERN_INFO "PXA CPU frequency change support initialized\n");
464 
465  return 0;
466 }
467 
468 static struct cpufreq_driver pxa_cpufreq_driver = {
469  .verify = pxa_verify_policy,
470  .target = pxa_set_target,
471  .init = pxa_cpufreq_init,
472  .get = pxa_cpufreq_get,
473  .name = "PXA2xx",
474 };
475 
476 static int __init pxa_cpu_init(void)
477 {
478  int ret = -ENODEV;
479  if (cpu_is_pxa25x() || cpu_is_pxa27x())
480  ret = cpufreq_register_driver(&pxa_cpufreq_driver);
481  return ret;
482 }
483 
484 static void __exit pxa_cpu_exit(void)
485 {
486  cpufreq_unregister_driver(&pxa_cpufreq_driver);
487 }
488 
489 
490 MODULE_AUTHOR("Intrinsyc Software Inc.");
491 MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
492 MODULE_LICENSE("GPL");
493 module_init(pxa_cpu_init);
494 module_exit(pxa_cpu_exit);