Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
cvmx-dpi-defs.h
Go to the documentation of this file.
1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT. See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_DPI_DEFS_H__
29 #define __CVMX_DPI_DEFS_H__
30 
31 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35 #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41 #define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43 #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44 #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45 #define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46 #define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47 #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48 #define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49 #define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50 #define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51 #define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52 #define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53 #define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54 #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
59 {
60  switch (cvmx_get_octeon_family()) {
61  case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
62  return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
63  case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
64  case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
65  case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
66 
67  if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
68  return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
69 
70  if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
71  return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
72  return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
73  case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
74  return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + (offset) * 8;
75  }
76  return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + (offset) * 8;
77 }
78 
79 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
80 
81 union cvmx_dpi_bist_status {
82  uint64_t u64;
83  struct cvmx_dpi_bist_status_s {
84 #ifdef __BIG_ENDIAN_BITFIELD
85  uint64_t reserved_47_63:17;
86  uint64_t bist:47;
87 #else
88  uint64_t bist:47;
89  uint64_t reserved_47_63:17;
90 #endif
91  } s;
92  struct cvmx_dpi_bist_status_s cn61xx;
93  struct cvmx_dpi_bist_status_cn63xx {
94 #ifdef __BIG_ENDIAN_BITFIELD
95  uint64_t reserved_45_63:19;
96  uint64_t bist:45;
97 #else
98  uint64_t bist:45;
99  uint64_t reserved_45_63:19;
100 #endif
101  } cn63xx;
102  struct cvmx_dpi_bist_status_cn63xxp1 {
103 #ifdef __BIG_ENDIAN_BITFIELD
104  uint64_t reserved_37_63:27;
105  uint64_t bist:37;
106 #else
107  uint64_t bist:37;
108  uint64_t reserved_37_63:27;
109 #endif
110  } cn63xxp1;
111  struct cvmx_dpi_bist_status_s cn66xx;
112  struct cvmx_dpi_bist_status_cn63xx cn68xx;
113  struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
114  struct cvmx_dpi_bist_status_s cnf71xx;
115 };
116 
117 union cvmx_dpi_ctl {
118  uint64_t u64;
119  struct cvmx_dpi_ctl_s {
120 #ifdef __BIG_ENDIAN_BITFIELD
121  uint64_t reserved_2_63:62;
122  uint64_t clk:1;
123  uint64_t en:1;
124 #else
125  uint64_t en:1;
126  uint64_t clk:1;
127  uint64_t reserved_2_63:62;
128 #endif
129  } s;
130  struct cvmx_dpi_ctl_cn61xx {
131 #ifdef __BIG_ENDIAN_BITFIELD
132  uint64_t reserved_1_63:63;
133  uint64_t en:1;
134 #else
135  uint64_t en:1;
136  uint64_t reserved_1_63:63;
137 #endif
138  } cn61xx;
139  struct cvmx_dpi_ctl_s cn63xx;
140  struct cvmx_dpi_ctl_s cn63xxp1;
141  struct cvmx_dpi_ctl_s cn66xx;
142  struct cvmx_dpi_ctl_s cn68xx;
143  struct cvmx_dpi_ctl_s cn68xxp1;
144  struct cvmx_dpi_ctl_cn61xx cnf71xx;
145 };
146 
147 union cvmx_dpi_dmax_counts {
148  uint64_t u64;
149  struct cvmx_dpi_dmax_counts_s {
150 #ifdef __BIG_ENDIAN_BITFIELD
151  uint64_t reserved_39_63:25;
152  uint64_t fcnt:7;
153  uint64_t dbell:32;
154 #else
155  uint64_t dbell:32;
156  uint64_t fcnt:7;
157  uint64_t reserved_39_63:25;
158 #endif
159  } s;
160  struct cvmx_dpi_dmax_counts_s cn61xx;
161  struct cvmx_dpi_dmax_counts_s cn63xx;
162  struct cvmx_dpi_dmax_counts_s cn63xxp1;
163  struct cvmx_dpi_dmax_counts_s cn66xx;
164  struct cvmx_dpi_dmax_counts_s cn68xx;
165  struct cvmx_dpi_dmax_counts_s cn68xxp1;
166  struct cvmx_dpi_dmax_counts_s cnf71xx;
167 };
168 
169 union cvmx_dpi_dmax_dbell {
170  uint64_t u64;
171  struct cvmx_dpi_dmax_dbell_s {
172 #ifdef __BIG_ENDIAN_BITFIELD
173  uint64_t reserved_16_63:48;
174  uint64_t dbell:16;
175 #else
176  uint64_t dbell:16;
177  uint64_t reserved_16_63:48;
178 #endif
179  } s;
180  struct cvmx_dpi_dmax_dbell_s cn61xx;
181  struct cvmx_dpi_dmax_dbell_s cn63xx;
182  struct cvmx_dpi_dmax_dbell_s cn63xxp1;
183  struct cvmx_dpi_dmax_dbell_s cn66xx;
184  struct cvmx_dpi_dmax_dbell_s cn68xx;
185  struct cvmx_dpi_dmax_dbell_s cn68xxp1;
186  struct cvmx_dpi_dmax_dbell_s cnf71xx;
187 };
188 
189 union cvmx_dpi_dmax_err_rsp_status {
190  uint64_t u64;
191  struct cvmx_dpi_dmax_err_rsp_status_s {
192 #ifdef __BIG_ENDIAN_BITFIELD
193  uint64_t reserved_6_63:58;
194  uint64_t status:6;
195 #else
196  uint64_t status:6;
197  uint64_t reserved_6_63:58;
198 #endif
199  } s;
200  struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
201  struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
202  struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
203  struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
204  struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
205 };
206 
207 union cvmx_dpi_dmax_ibuff_saddr {
208  uint64_t u64;
209  struct cvmx_dpi_dmax_ibuff_saddr_s {
210 #ifdef __BIG_ENDIAN_BITFIELD
211  uint64_t reserved_62_63:2;
212  uint64_t csize:14;
213  uint64_t reserved_41_47:7;
214  uint64_t idle:1;
215  uint64_t saddr:33;
216  uint64_t reserved_0_6:7;
217 #else
218  uint64_t reserved_0_6:7;
219  uint64_t saddr:33;
220  uint64_t idle:1;
221  uint64_t reserved_41_47:7;
222  uint64_t csize:14;
223  uint64_t reserved_62_63:2;
224 #endif
225  } s;
226  struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
227 #ifdef __BIG_ENDIAN_BITFIELD
228  uint64_t reserved_62_63:2;
229  uint64_t csize:14;
230  uint64_t reserved_41_47:7;
231  uint64_t idle:1;
232  uint64_t reserved_36_39:4;
233  uint64_t saddr:29;
234  uint64_t reserved_0_6:7;
235 #else
236  uint64_t reserved_0_6:7;
237  uint64_t saddr:29;
238  uint64_t reserved_36_39:4;
239  uint64_t idle:1;
240  uint64_t reserved_41_47:7;
241  uint64_t csize:14;
242  uint64_t reserved_62_63:2;
243 #endif
244  } cn61xx;
245  struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
246  struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
247  struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
248  struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
249  struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
250  struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
251 };
252 
253 union cvmx_dpi_dmax_iflight {
254  uint64_t u64;
255  struct cvmx_dpi_dmax_iflight_s {
256 #ifdef __BIG_ENDIAN_BITFIELD
257  uint64_t reserved_3_63:61;
258  uint64_t cnt:3;
259 #else
260  uint64_t cnt:3;
261  uint64_t reserved_3_63:61;
262 #endif
263  } s;
264  struct cvmx_dpi_dmax_iflight_s cn61xx;
265  struct cvmx_dpi_dmax_iflight_s cn66xx;
266  struct cvmx_dpi_dmax_iflight_s cn68xx;
267  struct cvmx_dpi_dmax_iflight_s cn68xxp1;
268  struct cvmx_dpi_dmax_iflight_s cnf71xx;
269 };
270 
271 union cvmx_dpi_dmax_naddr {
272  uint64_t u64;
273  struct cvmx_dpi_dmax_naddr_s {
274 #ifdef __BIG_ENDIAN_BITFIELD
275  uint64_t reserved_40_63:24;
276  uint64_t addr:40;
277 #else
278  uint64_t addr:40;
279  uint64_t reserved_40_63:24;
280 #endif
281  } s;
282  struct cvmx_dpi_dmax_naddr_cn61xx {
283 #ifdef __BIG_ENDIAN_BITFIELD
284  uint64_t reserved_36_63:28;
285  uint64_t addr:36;
286 #else
287  uint64_t addr:36;
288  uint64_t reserved_36_63:28;
289 #endif
290  } cn61xx;
291  struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
292  struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
293  struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
294  struct cvmx_dpi_dmax_naddr_s cn68xx;
295  struct cvmx_dpi_dmax_naddr_s cn68xxp1;
296  struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
297 };
298 
299 union cvmx_dpi_dmax_reqbnk0 {
300  uint64_t u64;
301  struct cvmx_dpi_dmax_reqbnk0_s {
302 #ifdef __BIG_ENDIAN_BITFIELD
303  uint64_t state:64;
304 #else
305  uint64_t state:64;
306 #endif
307  } s;
308  struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
309  struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
310  struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
311  struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
312  struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
313  struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
314  struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
315 };
316 
317 union cvmx_dpi_dmax_reqbnk1 {
318  uint64_t u64;
319  struct cvmx_dpi_dmax_reqbnk1_s {
320 #ifdef __BIG_ENDIAN_BITFIELD
321  uint64_t state:64;
322 #else
323  uint64_t state:64;
324 #endif
325  } s;
326  struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
327  struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
328  struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
329  struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
330  struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
331  struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
332  struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
333 };
334 
335 union cvmx_dpi_dma_control {
336  uint64_t u64;
337  struct cvmx_dpi_dma_control_s {
338 #ifdef __BIG_ENDIAN_BITFIELD
339  uint64_t reserved_62_63:2;
340  uint64_t dici_mode:1;
341  uint64_t pkt_en1:1;
342  uint64_t ffp_dis:1;
343  uint64_t commit_mode:1;
344  uint64_t pkt_hp:1;
345  uint64_t pkt_en:1;
346  uint64_t reserved_54_55:2;
347  uint64_t dma_enb:6;
348  uint64_t reserved_34_47:14;
349  uint64_t b0_lend:1;
350  uint64_t dwb_denb:1;
351  uint64_t dwb_ichk:9;
352  uint64_t fpa_que:3;
353  uint64_t o_add1:1;
354  uint64_t o_ro:1;
355  uint64_t o_ns:1;
356  uint64_t o_es:2;
357  uint64_t o_mode:1;
358  uint64_t reserved_0_13:14;
359 #else
360  uint64_t reserved_0_13:14;
361  uint64_t o_mode:1;
362  uint64_t o_es:2;
363  uint64_t o_ns:1;
364  uint64_t o_ro:1;
365  uint64_t o_add1:1;
366  uint64_t fpa_que:3;
367  uint64_t dwb_ichk:9;
368  uint64_t dwb_denb:1;
369  uint64_t b0_lend:1;
370  uint64_t reserved_34_47:14;
371  uint64_t dma_enb:6;
372  uint64_t reserved_54_55:2;
373  uint64_t pkt_en:1;
374  uint64_t pkt_hp:1;
375  uint64_t commit_mode:1;
376  uint64_t ffp_dis:1;
377  uint64_t pkt_en1:1;
378  uint64_t dici_mode:1;
379  uint64_t reserved_62_63:2;
380 #endif
381  } s;
382  struct cvmx_dpi_dma_control_s cn61xx;
383  struct cvmx_dpi_dma_control_cn63xx {
384 #ifdef __BIG_ENDIAN_BITFIELD
385  uint64_t reserved_61_63:3;
386  uint64_t pkt_en1:1;
387  uint64_t ffp_dis:1;
388  uint64_t commit_mode:1;
389  uint64_t pkt_hp:1;
390  uint64_t pkt_en:1;
391  uint64_t reserved_54_55:2;
392  uint64_t dma_enb:6;
393  uint64_t reserved_34_47:14;
394  uint64_t b0_lend:1;
395  uint64_t dwb_denb:1;
396  uint64_t dwb_ichk:9;
397  uint64_t fpa_que:3;
398  uint64_t o_add1:1;
399  uint64_t o_ro:1;
400  uint64_t o_ns:1;
401  uint64_t o_es:2;
402  uint64_t o_mode:1;
403  uint64_t reserved_0_13:14;
404 #else
405  uint64_t reserved_0_13:14;
406  uint64_t o_mode:1;
407  uint64_t o_es:2;
408  uint64_t o_ns:1;
409  uint64_t o_ro:1;
410  uint64_t o_add1:1;
411  uint64_t fpa_que:3;
412  uint64_t dwb_ichk:9;
413  uint64_t dwb_denb:1;
414  uint64_t b0_lend:1;
415  uint64_t reserved_34_47:14;
416  uint64_t dma_enb:6;
417  uint64_t reserved_54_55:2;
418  uint64_t pkt_en:1;
419  uint64_t pkt_hp:1;
420  uint64_t commit_mode:1;
421  uint64_t ffp_dis:1;
422  uint64_t pkt_en1:1;
423  uint64_t reserved_61_63:3;
424 #endif
425  } cn63xx;
426  struct cvmx_dpi_dma_control_cn63xxp1 {
427 #ifdef __BIG_ENDIAN_BITFIELD
428  uint64_t reserved_59_63:5;
429  uint64_t commit_mode:1;
430  uint64_t pkt_hp:1;
431  uint64_t pkt_en:1;
432  uint64_t reserved_54_55:2;
433  uint64_t dma_enb:6;
434  uint64_t reserved_34_47:14;
435  uint64_t b0_lend:1;
436  uint64_t dwb_denb:1;
437  uint64_t dwb_ichk:9;
438  uint64_t fpa_que:3;
439  uint64_t o_add1:1;
440  uint64_t o_ro:1;
441  uint64_t o_ns:1;
442  uint64_t o_es:2;
443  uint64_t o_mode:1;
444  uint64_t reserved_0_13:14;
445 #else
446  uint64_t reserved_0_13:14;
447  uint64_t o_mode:1;
448  uint64_t o_es:2;
449  uint64_t o_ns:1;
450  uint64_t o_ro:1;
451  uint64_t o_add1:1;
452  uint64_t fpa_que:3;
453  uint64_t dwb_ichk:9;
454  uint64_t dwb_denb:1;
455  uint64_t b0_lend:1;
456  uint64_t reserved_34_47:14;
457  uint64_t dma_enb:6;
458  uint64_t reserved_54_55:2;
459  uint64_t pkt_en:1;
460  uint64_t pkt_hp:1;
461  uint64_t commit_mode:1;
462  uint64_t reserved_59_63:5;
463 #endif
464  } cn63xxp1;
465  struct cvmx_dpi_dma_control_cn63xx cn66xx;
466  struct cvmx_dpi_dma_control_s cn68xx;
467  struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
468  struct cvmx_dpi_dma_control_s cnf71xx;
469 };
470 
471 union cvmx_dpi_dma_engx_en {
472  uint64_t u64;
473  struct cvmx_dpi_dma_engx_en_s {
474 #ifdef __BIG_ENDIAN_BITFIELD
475  uint64_t reserved_8_63:56;
476  uint64_t qen:8;
477 #else
478  uint64_t qen:8;
479  uint64_t reserved_8_63:56;
480 #endif
481  } s;
482  struct cvmx_dpi_dma_engx_en_s cn61xx;
483  struct cvmx_dpi_dma_engx_en_s cn63xx;
484  struct cvmx_dpi_dma_engx_en_s cn63xxp1;
485  struct cvmx_dpi_dma_engx_en_s cn66xx;
486  struct cvmx_dpi_dma_engx_en_s cn68xx;
487  struct cvmx_dpi_dma_engx_en_s cn68xxp1;
488  struct cvmx_dpi_dma_engx_en_s cnf71xx;
489 };
490 
491 union cvmx_dpi_dma_ppx_cnt {
492  uint64_t u64;
493  struct cvmx_dpi_dma_ppx_cnt_s {
494 #ifdef __BIG_ENDIAN_BITFIELD
495  uint64_t reserved_16_63:48;
496  uint64_t cnt:16;
497 #else
498  uint64_t cnt:16;
499  uint64_t reserved_16_63:48;
500 #endif
501  } s;
502  struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
503  struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
504  struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
505 };
506 
507 union cvmx_dpi_engx_buf {
508  uint64_t u64;
509  struct cvmx_dpi_engx_buf_s {
510 #ifdef __BIG_ENDIAN_BITFIELD
511  uint64_t reserved_37_63:27;
512  uint64_t compblks:5;
513  uint64_t reserved_9_31:23;
514  uint64_t base:5;
515  uint64_t blks:4;
516 #else
517  uint64_t blks:4;
518  uint64_t base:5;
519  uint64_t reserved_9_31:23;
520  uint64_t compblks:5;
521  uint64_t reserved_37_63:27;
522 #endif
523  } s;
524  struct cvmx_dpi_engx_buf_s cn61xx;
525  struct cvmx_dpi_engx_buf_cn63xx {
526 #ifdef __BIG_ENDIAN_BITFIELD
527  uint64_t reserved_8_63:56;
528  uint64_t base:4;
529  uint64_t blks:4;
530 #else
531  uint64_t blks:4;
532  uint64_t base:4;
533  uint64_t reserved_8_63:56;
534 #endif
535  } cn63xx;
536  struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
537  struct cvmx_dpi_engx_buf_s cn66xx;
538  struct cvmx_dpi_engx_buf_s cn68xx;
539  struct cvmx_dpi_engx_buf_s cn68xxp1;
540  struct cvmx_dpi_engx_buf_s cnf71xx;
541 };
542 
543 union cvmx_dpi_info_reg {
544  uint64_t u64;
545  struct cvmx_dpi_info_reg_s {
546 #ifdef __BIG_ENDIAN_BITFIELD
547  uint64_t reserved_8_63:56;
548  uint64_t ffp:4;
549  uint64_t reserved_2_3:2;
550  uint64_t ncb:1;
551  uint64_t rsl:1;
552 #else
553  uint64_t rsl:1;
554  uint64_t ncb:1;
555  uint64_t reserved_2_3:2;
556  uint64_t ffp:4;
557  uint64_t reserved_8_63:56;
558 #endif
559  } s;
560  struct cvmx_dpi_info_reg_s cn61xx;
561  struct cvmx_dpi_info_reg_s cn63xx;
562  struct cvmx_dpi_info_reg_cn63xxp1 {
563 #ifdef __BIG_ENDIAN_BITFIELD
564  uint64_t reserved_2_63:62;
565  uint64_t ncb:1;
566  uint64_t rsl:1;
567 #else
568  uint64_t rsl:1;
569  uint64_t ncb:1;
570  uint64_t reserved_2_63:62;
571 #endif
572  } cn63xxp1;
573  struct cvmx_dpi_info_reg_s cn66xx;
574  struct cvmx_dpi_info_reg_s cn68xx;
575  struct cvmx_dpi_info_reg_s cn68xxp1;
576  struct cvmx_dpi_info_reg_s cnf71xx;
577 };
578 
579 union cvmx_dpi_int_en {
580  uint64_t u64;
581  struct cvmx_dpi_int_en_s {
582 #ifdef __BIG_ENDIAN_BITFIELD
583  uint64_t reserved_28_63:36;
584  uint64_t sprt3_rst:1;
585  uint64_t sprt2_rst:1;
586  uint64_t sprt1_rst:1;
587  uint64_t sprt0_rst:1;
588  uint64_t reserved_23_23:1;
589  uint64_t req_badfil:1;
590  uint64_t req_inull:1;
591  uint64_t req_anull:1;
592  uint64_t req_undflw:1;
593  uint64_t req_ovrflw:1;
594  uint64_t req_badlen:1;
595  uint64_t req_badadr:1;
596  uint64_t dmadbo:8;
597  uint64_t reserved_2_7:6;
598  uint64_t nfovr:1;
599  uint64_t nderr:1;
600 #else
601  uint64_t nderr:1;
602  uint64_t nfovr:1;
603  uint64_t reserved_2_7:6;
604  uint64_t dmadbo:8;
605  uint64_t req_badadr:1;
606  uint64_t req_badlen:1;
607  uint64_t req_ovrflw:1;
608  uint64_t req_undflw:1;
609  uint64_t req_anull:1;
610  uint64_t req_inull:1;
611  uint64_t req_badfil:1;
612  uint64_t reserved_23_23:1;
613  uint64_t sprt0_rst:1;
614  uint64_t sprt1_rst:1;
615  uint64_t sprt2_rst:1;
616  uint64_t sprt3_rst:1;
617  uint64_t reserved_28_63:36;
618 #endif
619  } s;
620  struct cvmx_dpi_int_en_s cn61xx;
621  struct cvmx_dpi_int_en_cn63xx {
622 #ifdef __BIG_ENDIAN_BITFIELD
623  uint64_t reserved_26_63:38;
624  uint64_t sprt1_rst:1;
625  uint64_t sprt0_rst:1;
626  uint64_t reserved_23_23:1;
627  uint64_t req_badfil:1;
628  uint64_t req_inull:1;
629  uint64_t req_anull:1;
630  uint64_t req_undflw:1;
631  uint64_t req_ovrflw:1;
632  uint64_t req_badlen:1;
633  uint64_t req_badadr:1;
634  uint64_t dmadbo:8;
635  uint64_t reserved_2_7:6;
636  uint64_t nfovr:1;
637  uint64_t nderr:1;
638 #else
639  uint64_t nderr:1;
640  uint64_t nfovr:1;
641  uint64_t reserved_2_7:6;
642  uint64_t dmadbo:8;
643  uint64_t req_badadr:1;
644  uint64_t req_badlen:1;
645  uint64_t req_ovrflw:1;
646  uint64_t req_undflw:1;
647  uint64_t req_anull:1;
648  uint64_t req_inull:1;
649  uint64_t req_badfil:1;
650  uint64_t reserved_23_23:1;
651  uint64_t sprt0_rst:1;
652  uint64_t sprt1_rst:1;
653  uint64_t reserved_26_63:38;
654 #endif
655  } cn63xx;
656  struct cvmx_dpi_int_en_cn63xx cn63xxp1;
657  struct cvmx_dpi_int_en_s cn66xx;
658  struct cvmx_dpi_int_en_cn63xx cn68xx;
659  struct cvmx_dpi_int_en_cn63xx cn68xxp1;
660  struct cvmx_dpi_int_en_s cnf71xx;
661 };
662 
663 union cvmx_dpi_int_reg {
664  uint64_t u64;
665  struct cvmx_dpi_int_reg_s {
666 #ifdef __BIG_ENDIAN_BITFIELD
667  uint64_t reserved_28_63:36;
668  uint64_t sprt3_rst:1;
669  uint64_t sprt2_rst:1;
670  uint64_t sprt1_rst:1;
671  uint64_t sprt0_rst:1;
672  uint64_t reserved_23_23:1;
673  uint64_t req_badfil:1;
674  uint64_t req_inull:1;
675  uint64_t req_anull:1;
676  uint64_t req_undflw:1;
677  uint64_t req_ovrflw:1;
678  uint64_t req_badlen:1;
679  uint64_t req_badadr:1;
680  uint64_t dmadbo:8;
681  uint64_t reserved_2_7:6;
682  uint64_t nfovr:1;
683  uint64_t nderr:1;
684 #else
685  uint64_t nderr:1;
686  uint64_t nfovr:1;
687  uint64_t reserved_2_7:6;
688  uint64_t dmadbo:8;
689  uint64_t req_badadr:1;
690  uint64_t req_badlen:1;
691  uint64_t req_ovrflw:1;
692  uint64_t req_undflw:1;
693  uint64_t req_anull:1;
694  uint64_t req_inull:1;
695  uint64_t req_badfil:1;
696  uint64_t reserved_23_23:1;
697  uint64_t sprt0_rst:1;
698  uint64_t sprt1_rst:1;
699  uint64_t sprt2_rst:1;
700  uint64_t sprt3_rst:1;
701  uint64_t reserved_28_63:36;
702 #endif
703  } s;
704  struct cvmx_dpi_int_reg_s cn61xx;
705  struct cvmx_dpi_int_reg_cn63xx {
706 #ifdef __BIG_ENDIAN_BITFIELD
707  uint64_t reserved_26_63:38;
708  uint64_t sprt1_rst:1;
709  uint64_t sprt0_rst:1;
710  uint64_t reserved_23_23:1;
711  uint64_t req_badfil:1;
712  uint64_t req_inull:1;
713  uint64_t req_anull:1;
714  uint64_t req_undflw:1;
715  uint64_t req_ovrflw:1;
716  uint64_t req_badlen:1;
717  uint64_t req_badadr:1;
718  uint64_t dmadbo:8;
719  uint64_t reserved_2_7:6;
720  uint64_t nfovr:1;
721  uint64_t nderr:1;
722 #else
723  uint64_t nderr:1;
724  uint64_t nfovr:1;
725  uint64_t reserved_2_7:6;
726  uint64_t dmadbo:8;
727  uint64_t req_badadr:1;
728  uint64_t req_badlen:1;
729  uint64_t req_ovrflw:1;
730  uint64_t req_undflw:1;
731  uint64_t req_anull:1;
732  uint64_t req_inull:1;
733  uint64_t req_badfil:1;
734  uint64_t reserved_23_23:1;
735  uint64_t sprt0_rst:1;
736  uint64_t sprt1_rst:1;
737  uint64_t reserved_26_63:38;
738 #endif
739  } cn63xx;
740  struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
741  struct cvmx_dpi_int_reg_s cn66xx;
742  struct cvmx_dpi_int_reg_cn63xx cn68xx;
743  struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
744  struct cvmx_dpi_int_reg_s cnf71xx;
745 };
746 
747 union cvmx_dpi_ncbx_cfg {
748  uint64_t u64;
749  struct cvmx_dpi_ncbx_cfg_s {
750 #ifdef __BIG_ENDIAN_BITFIELD
751  uint64_t reserved_6_63:58;
752  uint64_t molr:6;
753 #else
754  uint64_t molr:6;
755  uint64_t reserved_6_63:58;
756 #endif
757  } s;
758  struct cvmx_dpi_ncbx_cfg_s cn61xx;
759  struct cvmx_dpi_ncbx_cfg_s cn66xx;
760  struct cvmx_dpi_ncbx_cfg_s cn68xx;
761  struct cvmx_dpi_ncbx_cfg_s cnf71xx;
762 };
763 
764 union cvmx_dpi_pint_info {
765  uint64_t u64;
766  struct cvmx_dpi_pint_info_s {
767 #ifdef __BIG_ENDIAN_BITFIELD
768  uint64_t reserved_14_63:50;
769  uint64_t iinfo:6;
770  uint64_t reserved_6_7:2;
771  uint64_t sinfo:6;
772 #else
773  uint64_t sinfo:6;
774  uint64_t reserved_6_7:2;
775  uint64_t iinfo:6;
776  uint64_t reserved_14_63:50;
777 #endif
778  } s;
779  struct cvmx_dpi_pint_info_s cn61xx;
780  struct cvmx_dpi_pint_info_s cn63xx;
781  struct cvmx_dpi_pint_info_s cn63xxp1;
782  struct cvmx_dpi_pint_info_s cn66xx;
783  struct cvmx_dpi_pint_info_s cn68xx;
784  struct cvmx_dpi_pint_info_s cn68xxp1;
785  struct cvmx_dpi_pint_info_s cnf71xx;
786 };
787 
788 union cvmx_dpi_pkt_err_rsp {
789  uint64_t u64;
790  struct cvmx_dpi_pkt_err_rsp_s {
791 #ifdef __BIG_ENDIAN_BITFIELD
792  uint64_t reserved_1_63:63;
793  uint64_t pkterr:1;
794 #else
795  uint64_t pkterr:1;
796  uint64_t reserved_1_63:63;
797 #endif
798  } s;
799  struct cvmx_dpi_pkt_err_rsp_s cn61xx;
800  struct cvmx_dpi_pkt_err_rsp_s cn63xx;
801  struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
802  struct cvmx_dpi_pkt_err_rsp_s cn66xx;
803  struct cvmx_dpi_pkt_err_rsp_s cn68xx;
804  struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
805  struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
806 };
807 
808 union cvmx_dpi_req_err_rsp {
809  uint64_t u64;
810  struct cvmx_dpi_req_err_rsp_s {
811 #ifdef __BIG_ENDIAN_BITFIELD
812  uint64_t reserved_8_63:56;
813  uint64_t qerr:8;
814 #else
815  uint64_t qerr:8;
816  uint64_t reserved_8_63:56;
817 #endif
818  } s;
819  struct cvmx_dpi_req_err_rsp_s cn61xx;
820  struct cvmx_dpi_req_err_rsp_s cn63xx;
821  struct cvmx_dpi_req_err_rsp_s cn63xxp1;
822  struct cvmx_dpi_req_err_rsp_s cn66xx;
823  struct cvmx_dpi_req_err_rsp_s cn68xx;
824  struct cvmx_dpi_req_err_rsp_s cn68xxp1;
825  struct cvmx_dpi_req_err_rsp_s cnf71xx;
826 };
827 
828 union cvmx_dpi_req_err_rsp_en {
829  uint64_t u64;
830  struct cvmx_dpi_req_err_rsp_en_s {
831 #ifdef __BIG_ENDIAN_BITFIELD
832  uint64_t reserved_8_63:56;
833  uint64_t en:8;
834 #else
835  uint64_t en:8;
836  uint64_t reserved_8_63:56;
837 #endif
838  } s;
839  struct cvmx_dpi_req_err_rsp_en_s cn61xx;
840  struct cvmx_dpi_req_err_rsp_en_s cn63xx;
841  struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
842  struct cvmx_dpi_req_err_rsp_en_s cn66xx;
843  struct cvmx_dpi_req_err_rsp_en_s cn68xx;
844  struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
845  struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
846 };
847 
848 union cvmx_dpi_req_err_rst {
849  uint64_t u64;
850  struct cvmx_dpi_req_err_rst_s {
851 #ifdef __BIG_ENDIAN_BITFIELD
852  uint64_t reserved_8_63:56;
853  uint64_t qerr:8;
854 #else
855  uint64_t qerr:8;
856  uint64_t reserved_8_63:56;
857 #endif
858  } s;
859  struct cvmx_dpi_req_err_rst_s cn61xx;
860  struct cvmx_dpi_req_err_rst_s cn63xx;
861  struct cvmx_dpi_req_err_rst_s cn63xxp1;
862  struct cvmx_dpi_req_err_rst_s cn66xx;
863  struct cvmx_dpi_req_err_rst_s cn68xx;
864  struct cvmx_dpi_req_err_rst_s cn68xxp1;
865  struct cvmx_dpi_req_err_rst_s cnf71xx;
866 };
867 
868 union cvmx_dpi_req_err_rst_en {
869  uint64_t u64;
870  struct cvmx_dpi_req_err_rst_en_s {
871 #ifdef __BIG_ENDIAN_BITFIELD
872  uint64_t reserved_8_63:56;
873  uint64_t en:8;
874 #else
875  uint64_t en:8;
876  uint64_t reserved_8_63:56;
877 #endif
878  } s;
879  struct cvmx_dpi_req_err_rst_en_s cn61xx;
880  struct cvmx_dpi_req_err_rst_en_s cn63xx;
881  struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
882  struct cvmx_dpi_req_err_rst_en_s cn66xx;
883  struct cvmx_dpi_req_err_rst_en_s cn68xx;
884  struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
885  struct cvmx_dpi_req_err_rst_en_s cnf71xx;
886 };
887 
888 union cvmx_dpi_req_err_skip_comp {
889  uint64_t u64;
890  struct cvmx_dpi_req_err_skip_comp_s {
891 #ifdef __BIG_ENDIAN_BITFIELD
892  uint64_t reserved_24_63:40;
893  uint64_t en_rst:8;
894  uint64_t reserved_8_15:8;
895  uint64_t en_rsp:8;
896 #else
897  uint64_t en_rsp:8;
898  uint64_t reserved_8_15:8;
899  uint64_t en_rst:8;
900  uint64_t reserved_24_63:40;
901 #endif
902  } s;
903  struct cvmx_dpi_req_err_skip_comp_s cn61xx;
904  struct cvmx_dpi_req_err_skip_comp_s cn66xx;
905  struct cvmx_dpi_req_err_skip_comp_s cn68xx;
906  struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
907  struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
908 };
909 
910 union cvmx_dpi_req_gbl_en {
911  uint64_t u64;
912  struct cvmx_dpi_req_gbl_en_s {
913 #ifdef __BIG_ENDIAN_BITFIELD
914  uint64_t reserved_8_63:56;
915  uint64_t qen:8;
916 #else
917  uint64_t qen:8;
918  uint64_t reserved_8_63:56;
919 #endif
920  } s;
921  struct cvmx_dpi_req_gbl_en_s cn61xx;
922  struct cvmx_dpi_req_gbl_en_s cn63xx;
923  struct cvmx_dpi_req_gbl_en_s cn63xxp1;
924  struct cvmx_dpi_req_gbl_en_s cn66xx;
925  struct cvmx_dpi_req_gbl_en_s cn68xx;
926  struct cvmx_dpi_req_gbl_en_s cn68xxp1;
927  struct cvmx_dpi_req_gbl_en_s cnf71xx;
928 };
929 
930 union cvmx_dpi_sli_prtx_cfg {
931  uint64_t u64;
932  struct cvmx_dpi_sli_prtx_cfg_s {
933 #ifdef __BIG_ENDIAN_BITFIELD
934  uint64_t reserved_25_63:39;
935  uint64_t halt:1;
936  uint64_t qlm_cfg:4;
937  uint64_t reserved_17_19:3;
938  uint64_t rd_mode:1;
939  uint64_t reserved_14_15:2;
940  uint64_t molr:6;
941  uint64_t mps_lim:1;
942  uint64_t reserved_5_6:2;
943  uint64_t mps:1;
944  uint64_t mrrs_lim:1;
945  uint64_t reserved_2_2:1;
946  uint64_t mrrs:2;
947 #else
948  uint64_t mrrs:2;
949  uint64_t reserved_2_2:1;
950  uint64_t mrrs_lim:1;
951  uint64_t mps:1;
952  uint64_t reserved_5_6:2;
953  uint64_t mps_lim:1;
954  uint64_t molr:6;
955  uint64_t reserved_14_15:2;
956  uint64_t rd_mode:1;
957  uint64_t reserved_17_19:3;
958  uint64_t qlm_cfg:4;
959  uint64_t halt:1;
960  uint64_t reserved_25_63:39;
961 #endif
962  } s;
963  struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
964  struct cvmx_dpi_sli_prtx_cfg_cn63xx {
965 #ifdef __BIG_ENDIAN_BITFIELD
966  uint64_t reserved_25_63:39;
967  uint64_t halt:1;
968  uint64_t reserved_21_23:3;
969  uint64_t qlm_cfg:1;
970  uint64_t reserved_17_19:3;
971  uint64_t rd_mode:1;
972  uint64_t reserved_14_15:2;
973  uint64_t molr:6;
974  uint64_t mps_lim:1;
975  uint64_t reserved_5_6:2;
976  uint64_t mps:1;
977  uint64_t mrrs_lim:1;
978  uint64_t reserved_2_2:1;
979  uint64_t mrrs:2;
980 #else
981  uint64_t mrrs:2;
982  uint64_t reserved_2_2:1;
983  uint64_t mrrs_lim:1;
984  uint64_t mps:1;
985  uint64_t reserved_5_6:2;
986  uint64_t mps_lim:1;
987  uint64_t molr:6;
988  uint64_t reserved_14_15:2;
989  uint64_t rd_mode:1;
990  uint64_t reserved_17_19:3;
991  uint64_t qlm_cfg:1;
992  uint64_t reserved_21_23:3;
993  uint64_t halt:1;
994  uint64_t reserved_25_63:39;
995 #endif
996  } cn63xx;
997  struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
998  struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
999  struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
1000  struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
1001  struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
1002 };
1003 
1004 union cvmx_dpi_sli_prtx_err {
1005  uint64_t u64;
1006  struct cvmx_dpi_sli_prtx_err_s {
1007 #ifdef __BIG_ENDIAN_BITFIELD
1008  uint64_t addr:61;
1009  uint64_t reserved_0_2:3;
1010 #else
1011  uint64_t reserved_0_2:3;
1012  uint64_t addr:61;
1013 #endif
1014  } s;
1015  struct cvmx_dpi_sli_prtx_err_s cn61xx;
1016  struct cvmx_dpi_sli_prtx_err_s cn63xx;
1017  struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
1018  struct cvmx_dpi_sli_prtx_err_s cn66xx;
1019  struct cvmx_dpi_sli_prtx_err_s cn68xx;
1020  struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
1021  struct cvmx_dpi_sli_prtx_err_s cnf71xx;
1022 };
1023 
1024 union cvmx_dpi_sli_prtx_err_info {
1025  uint64_t u64;
1026  struct cvmx_dpi_sli_prtx_err_info_s {
1027 #ifdef __BIG_ENDIAN_BITFIELD
1028  uint64_t reserved_9_63:55;
1029  uint64_t lock:1;
1030  uint64_t reserved_5_7:3;
1031  uint64_t type:1;
1032  uint64_t reserved_3_3:1;
1033  uint64_t reqq:3;
1034 #else
1035  uint64_t reqq:3;
1036  uint64_t reserved_3_3:1;
1037  uint64_t type:1;
1038  uint64_t reserved_5_7:3;
1039  uint64_t lock:1;
1040  uint64_t reserved_9_63:55;
1041 #endif
1042  } s;
1043  struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
1044  struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
1045  struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
1046  struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
1047  struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
1048  struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
1049  struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;
1050 };
1051 
1052 #endif
Generated on Thu Jan 10 2013 13:10:06 for Linux Kernel by   doxygen 1.8.2