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cvmx-iob-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT. See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_IOB_DEFS_H__
29 #define __CVMX_IOB_DEFS_H__
30 
31 #define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
32 #define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
33 #define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
34 #define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
35 #define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
36 #define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
37 #define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
38 #define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
39 #define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
40 #define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
41 #define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
42 #define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
43 #define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
44 #define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
45 #define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
46 #define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
47 #define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
48 #define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
49 #define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
50 #define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
51 #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
52 #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
53 #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
54 #define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
55 #define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
56 #define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
57 #define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
58 #define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
59 #define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
60 #define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
61 #define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
62 #define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
63 #define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
64 #define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
65 
69 #ifdef __BIG_ENDIAN_BITFIELD
71  uint64_t ibd:1;
72  uint64_t icd:1;
73 #else
77 #endif
78  } s;
80 #ifdef __BIG_ENDIAN_BITFIELD
82  uint64_t icnrcb:1;
83  uint64_t icr0:1;
84  uint64_t icr1:1;
85  uint64_t icnr1:1;
86  uint64_t icnr0:1;
87  uint64_t ibdr0:1;
88  uint64_t ibdr1:1;
89  uint64_t ibr0:1;
90  uint64_t ibr1:1;
91  uint64_t icnrt:1;
92  uint64_t ibrq0:1;
93  uint64_t ibrq1:1;
94  uint64_t icrn0:1;
95  uint64_t icrn1:1;
96  uint64_t icrp0:1;
97  uint64_t icrp1:1;
98  uint64_t ibd:1;
99  uint64_t icd:1;
100 #else
120 #endif
121  } cn30xx;
133 #ifdef __BIG_ENDIAN_BITFIELD
135  uint64_t xmdfif:1;
136  uint64_t xmcfif:1;
137  uint64_t iorfif:1;
138  uint64_t rsdfif:1;
139  uint64_t iocfif:1;
140  uint64_t icnrcb:1;
141  uint64_t icr0:1;
142  uint64_t icr1:1;
143  uint64_t icnr1:1;
144  uint64_t icnr0:1;
145  uint64_t ibdr0:1;
146  uint64_t ibdr1:1;
147  uint64_t ibr0:1;
148  uint64_t ibr1:1;
149  uint64_t icnrt:1;
150  uint64_t ibrq0:1;
151  uint64_t ibrq1:1;
152  uint64_t icrn0:1;
153  uint64_t icrn1:1;
154  uint64_t icrp0:1;
155  uint64_t icrp1:1;
156  uint64_t ibd:1;
157  uint64_t icd:1;
158 #else
183 #endif
184  } cn61xx;
189 #ifdef __BIG_ENDIAN_BITFIELD
191  uint64_t xmdfif:1;
192  uint64_t xmcfif:1;
193  uint64_t iorfif:1;
194  uint64_t rsdfif:1;
195  uint64_t iocfif:1;
196  uint64_t icnrcb:1;
197  uint64_t icr0:1;
198  uint64_t icr1:1;
199  uint64_t icnr0:1;
200  uint64_t ibr0:1;
201  uint64_t ibr1:1;
202  uint64_t icnrt:1;
203  uint64_t ibrq0:1;
204  uint64_t ibrq1:1;
205  uint64_t icrn0:1;
206  uint64_t icrn1:1;
207  uint64_t ibd:1;
208  uint64_t icd:1;
209 #else
229 #endif
230  } cn68xx;
233 };
234 
238 #ifdef __BIG_ENDIAN_BITFIELD
240  uint64_t fif_dly:1;
241  uint64_t xmc_per:4;
243  uint64_t outb_mat:1;
244  uint64_t inb_mat:1;
245  uint64_t pko_enb:1;
246  uint64_t dwb_enb:1;
247  uint64_t fau_end:1;
248 #else
258 #endif
259  } s;
261 #ifdef __BIG_ENDIAN_BITFIELD
263  uint64_t outb_mat:1;
264  uint64_t inb_mat:1;
265  uint64_t pko_enb:1;
266  uint64_t dwb_enb:1;
267  uint64_t fau_end:1;
268 #else
275 #endif
276  } cn30xx;
282 #ifdef __BIG_ENDIAN_BITFIELD
284  uint64_t rr_mode:1;
285  uint64_t outb_mat:1;
286  uint64_t inb_mat:1;
287  uint64_t pko_enb:1;
288  uint64_t dwb_enb:1;
289  uint64_t fau_end:1;
290 #else
298 #endif
299  } cn52xx;
306 #ifdef __BIG_ENDIAN_BITFIELD
308  uint64_t fif_dly:1;
309  uint64_t xmc_per:4;
310  uint64_t rr_mode:1;
311  uint64_t outb_mat:1;
312  uint64_t inb_mat:1;
313  uint64_t pko_enb:1;
314  uint64_t dwb_enb:1;
315  uint64_t fau_end:1;
316 #else
326 #endif
327  } cn61xx;
329 #ifdef __BIG_ENDIAN_BITFIELD
331  uint64_t xmc_per:4;
332  uint64_t rr_mode:1;
333  uint64_t outb_mat:1;
334  uint64_t inb_mat:1;
335  uint64_t pko_enb:1;
336  uint64_t dwb_enb:1;
337  uint64_t fau_end:1;
338 #else
347 #endif
348  } cn63xx;
352 #ifdef __BIG_ENDIAN_BITFIELD
354  uint64_t fif_dly:1;
355  uint64_t xmc_per:4;
356  uint64_t rsvr5:1;
357  uint64_t outb_mat:1;
358  uint64_t inb_mat:1;
359  uint64_t pko_enb:1;
360  uint64_t dwb_enb:1;
361  uint64_t fau_end:1;
362 #else
372 #endif
373  } cn68xx;
376 };
377 
381 #ifdef __BIG_ENDIAN_BITFIELD
383  uint64_t cnt_enb:1;
384  uint64_t cnt_val:15;
385 #else
389 #endif
390  } s;
404 };
405 
409 #ifdef __BIG_ENDIAN_BITFIELD
411  uint64_t tout_enb:1;
412  uint64_t tout_val:12;
413 #else
417 #endif
418  } s;
437 };
438 
442 #ifdef __BIG_ENDIAN_BITFIELD
444  uint64_t cnt_enb:1;
445  uint64_t cnt_val:15;
446 #else
450 #endif
451  } s;
465 };
466 
470 #ifdef __BIG_ENDIAN_BITFIELD
472  uint64_t mask:8;
473  uint64_t opc:4;
474  uint64_t dst:9;
475  uint64_t src:8;
476 #else
482 #endif
483  } s;
502 };
503 
507 #ifdef __BIG_ENDIAN_BITFIELD
509  uint64_t mask:8;
510  uint64_t opc:4;
511  uint64_t dst:9;
512  uint64_t src:8;
513 #else
519 #endif
520  } s;
539 };
540 
544 #ifdef __BIG_ENDIAN_BITFIELD
545  uint64_t data:64;
546 #else
548 #endif
549  } s;
568 };
569 
573 #ifdef __BIG_ENDIAN_BITFIELD
574  uint64_t data:64;
575 #else
577 #endif
578  } s;
597 };
598 
602 #ifdef __BIG_ENDIAN_BITFIELD
604  uint64_t p_dat:1;
605  uint64_t np_dat:1;
606  uint64_t p_eop:1;
607  uint64_t p_sop:1;
608  uint64_t np_eop:1;
609  uint64_t np_sop:1;
610 #else
618 #endif
619  } s;
621 #ifdef __BIG_ENDIAN_BITFIELD
623  uint64_t p_eop:1;
624  uint64_t p_sop:1;
625  uint64_t np_eop:1;
626  uint64_t np_sop:1;
627 #else
633 #endif
634  } cn30xx;
650 #ifdef __BIG_ENDIAN_BITFIELD
652 #else
654 #endif
655  } cn68xx;
658 };
659 
663 #ifdef __BIG_ENDIAN_BITFIELD
665  uint64_t p_dat:1;
666  uint64_t np_dat:1;
667  uint64_t p_eop:1;
668  uint64_t p_sop:1;
669  uint64_t np_eop:1;
670  uint64_t np_sop:1;
671 #else
679 #endif
680  } s;
682 #ifdef __BIG_ENDIAN_BITFIELD
684  uint64_t p_eop:1;
685  uint64_t p_sop:1;
686  uint64_t np_eop:1;
687  uint64_t np_sop:1;
688 #else
694 #endif
695  } cn30xx;
711 #ifdef __BIG_ENDIAN_BITFIELD
713 #else
715 #endif
716  } cn68xx;
719 };
720 
724 #ifdef __BIG_ENDIAN_BITFIELD
726  uint64_t cnt_enb:1;
727  uint64_t cnt_val:15;
728 #else
732 #endif
733  } s;
747 };
748 
752 #ifdef __BIG_ENDIAN_BITFIELD
754  uint64_t cnt_enb:1;
755  uint64_t cnt_val:15;
756 #else
760 #endif
761  } s;
775 };
776 
780 #ifdef __BIG_ENDIAN_BITFIELD
782  uint64_t cnt_enb:1;
783  uint64_t cnt_val:15;
784 #else
788 #endif
789  } s;
805 };
806 
810 #ifdef __BIG_ENDIAN_BITFIELD
812  uint64_t mask:8;
813  uint64_t eot:1;
814  uint64_t dst:8;
815  uint64_t src:9;
816 #else
822 #endif
823  } s;
842 };
843 
847 #ifdef __BIG_ENDIAN_BITFIELD
849  uint64_t mask:8;
850  uint64_t eot:1;
851  uint64_t dst:8;
852  uint64_t src:9;
853 #else
859 #endif
860  } s;
879 };
880 
884 #ifdef __BIG_ENDIAN_BITFIELD
885  uint64_t data:64;
886 #else
888 #endif
889  } s;
908 };
909 
913 #ifdef __BIG_ENDIAN_BITFIELD
914  uint64_t data:64;
915 #else
917 #endif
918  } s;
937 };
938 
942 #ifdef __BIG_ENDIAN_BITFIELD
944  uint64_t cnt_enb:1;
945  uint64_t cnt_val:15;
946 #else
950 #endif
951  } s;
967 };
968 
972 #ifdef __BIG_ENDIAN_BITFIELD
974  uint64_t cnt_enb:1;
975  uint64_t cnt_val:15;
976 #else
980 #endif
981  } s;
997 };
998 
1002 #ifdef __BIG_ENDIAN_BITFIELD
1004  uint64_t cnt_enb:1;
1005  uint64_t cnt_val:15;
1006 #else
1010 #endif
1011  } s;
1025 };
1026 
1030 #ifdef __BIG_ENDIAN_BITFIELD
1032  uint64_t vport:6;
1033  uint64_t port:6;
1034 #else
1038 #endif
1039  } s;
1041 #ifdef __BIG_ENDIAN_BITFIELD
1043  uint64_t port:6;
1044 #else
1047 #endif
1048  } cn30xx;
1064 };
1065 
1069 #ifdef __BIG_ENDIAN_BITFIELD
1071  uint64_t ncb_rd:3;
1072  uint64_t ncb_wr:3;
1073 #else
1077 #endif
1078  } s;
1080 #ifdef __BIG_ENDIAN_BITFIELD
1082  uint64_t pko_rd:3;
1083  uint64_t ncb_rd:3;
1084  uint64_t ncb_wr:3;
1085 #else
1090 #endif
1091  } cn52xx;
1097 #ifdef __BIG_ENDIAN_BITFIELD
1099  uint64_t dwb:3;
1100  uint64_t ncb_rd:3;
1101  uint64_t ncb_wr:3;
1102 #else
1107 #endif
1108  } cn68xx;
1111 };
1112 
1116 #ifdef __BIG_ENDIAN_BITFIELD
1118  uint64_t crd:7;
1119 #else
1122 #endif
1123  } s;
1126 };
1127 
1131 #ifdef __BIG_ENDIAN_BITFIELD
1133  uint64_t crd:7;
1134 #else
1137 #endif
1138  } s;
1141 };
1142 
1146 #ifdef __BIG_ENDIAN_BITFIELD
1148  uint64_t crd:7;
1149 #else
1152 #endif
1153  } s;
1156 };
1157 
1161 #ifdef __BIG_ENDIAN_BITFIELD
1163  uint64_t crd:7;
1164 #else
1167 #endif
1168  } s;
1171 };
1172 
1176 #ifdef __BIG_ENDIAN_BITFIELD
1178  uint64_t crd:7;
1179 #else
1182 #endif
1183  } s;
1186 };
1187 
1191 #ifdef __BIG_ENDIAN_BITFIELD
1193  uint64_t crd:7;
1194 #else
1197 #endif
1198  } s;
1201 };
1202 
1206 #ifdef __BIG_ENDIAN_BITFIELD
1208  uint64_t crd:7;
1209 #else
1212 #endif
1213  } s;
1216 };
1217 
1221 #ifdef __BIG_ENDIAN_BITFIELD
1223  uint64_t crd:7;
1224 #else
1227 #endif
1228  } s;
1231 };
1232 
1236 #ifdef __BIG_ENDIAN_BITFIELD
1238  uint64_t crd:7;
1239 #else
1242 #endif
1243  } s;
1246 };
1247 
1251 #ifdef __BIG_ENDIAN_BITFIELD
1253  uint64_t crd:7;
1254 #else
1257 #endif
1258  } s;
1261 };
1262 
1266 #ifdef __BIG_ENDIAN_BITFIELD
1268  uint64_t crd:7;
1269 #else
1272 #endif
1273  } s;
1276 };
1277 
1278 #endif