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cvmx-l2c-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
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11  * published by the Free Software Foundation.
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26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_L2C_DEFS_H__
29 #define __CVMX_L2C_DEFS_H__
30 
31 #define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
32 #define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
33 #define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
34 #define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
35 #define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
36 #define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull)
37 #define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull) + ((block_id) & 3) * 0x40000ull)
38 #define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull) + ((block_id) & 3) * 0x40000ull)
39 #define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
40 #define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
41 #define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
42 #define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
43 #define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
44 #define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 8191) * 8)
45 #define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull) + ((block_id) & 3) * 0x40000ull)
46 #define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull) + ((block_id) & 3) * 0x40000ull)
47 #define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull) + ((block_id) & 3) * 0x40000ull)
48 #define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
49 #define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
50 #define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
51 #define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
52 #define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
53 #define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
54 #define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
55 #define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
56 #define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
57 #define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
58 #define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
59 #define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull))
60 #define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull))
61 #define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull))
62 #define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
63 #define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
64 #define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
65 #define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
66 #define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
67 #define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
68 #define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
69 #define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
70 #define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
71 #define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
72 #define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
73 #define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
74 #define CVMX_L2C_QOS_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080880200ull) + ((offset) & 1) * 8)
75 #define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 31) * 8)
76 #define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
77 #define CVMX_L2C_RSCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800410ull) + ((offset) & 3) * 64)
78 #define CVMX_L2C_RSDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800418ull) + ((offset) & 3) * 64)
79 #define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
80 #define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
81 #define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
82 #define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
83 #define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
84 #define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull) + ((block_id) & 3) * 0x40000ull)
85 #define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull) + ((block_id) & 3) * 0x40000ull)
86 #define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull) + ((block_id) & 3) * 0x40000ull)
87 #define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull) + ((block_id) & 3) * 0x40000ull)
88 #define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull) + ((block_id) & 3) * 0x40000ull)
89 #define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull) + ((block_id) & 3) * 0x40000ull)
90 #define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull) + ((block_id) & 3) * 0x40000ull)
91 #define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull) + ((block_id) & 3) * 0x40000ull)
92 #define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull) + ((block_id) & 3) * 0x40000ull)
93 #define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull) + ((block_id) & 3) * 0x40000ull)
94 #define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
95 #define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
96 #define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
97 #define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
98 #define CVMX_L2C_VIRTID_IOBX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0200ull) + ((offset) & 1) * 8)
99 #define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 31) * 8)
100 #define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
101 #define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
102 #define CVMX_L2C_WPAR_IOBX(offset) (CVMX_ADD_IO_SEG(0x0001180080840200ull) + ((offset) & 1) * 8)
103 #define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 31) * 8)
104 #define CVMX_L2C_XMCX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800400ull) + ((offset) & 3) * 64)
105 #define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
106 #define CVMX_L2C_XMDX_PFC(offset) (CVMX_ADD_IO_SEG(0x0001180080800408ull) + ((offset) & 3) * 64)
107 
111 #ifdef __BIG_ENDIAN_BITFIELD
113  uint64_t maxdram:4;
115  uint64_t disable:1;
116 #else
121 #endif
122  } s;
129 };
130 
133  struct cvmx_l2c_bst_s {
134 #ifdef __BIG_ENDIAN_BITFIELD
135  uint64_t dutfl:32;
136  uint64_t rbffl:4;
137  uint64_t xbffl:4;
138  uint64_t tdpfl:4;
139  uint64_t ioccmdfl:4;
140  uint64_t iocdatfl:4;
141  uint64_t dutresfl:4;
142  uint64_t vrtfl:4;
143  uint64_t tdffl:4;
144 #else
154 #endif
155  } s;
157 #ifdef __BIG_ENDIAN_BITFIELD
159  uint64_t dutfl:4;
161  uint64_t ioccmdfl:1;
163  uint64_t iocdatfl:1;
165  uint64_t dutresfl:1;
167  uint64_t vrtfl:1;
169  uint64_t tdffl:1;
170 #else
183 #endif
184  } cn61xx;
186 #ifdef __BIG_ENDIAN_BITFIELD
188  uint64_t dutfl:6;
190  uint64_t ioccmdfl:1;
192  uint64_t iocdatfl:1;
194  uint64_t dutresfl:1;
196  uint64_t vrtfl:1;
198  uint64_t tdffl:1;
199 #else
212 #endif
213  } cn63xx;
216 #ifdef __BIG_ENDIAN_BITFIELD
218  uint64_t dutfl:10;
220  uint64_t ioccmdfl:1;
222  uint64_t iocdatfl:1;
224  uint64_t dutresfl:1;
226  uint64_t vrtfl:1;
228  uint64_t tdffl:1;
229 #else
242 #endif
243  } cn66xx;
247 };
248 
252 #ifdef __BIG_ENDIAN_BITFIELD
254  uint64_t dtbnk:1;
255  uint64_t wlb_msk:4;
256  uint64_t dtcnt:13;
257  uint64_t dt:1;
258  uint64_t stin_msk:1;
259  uint64_t wlb_dat:4;
260 #else
268 #endif
269  } s;
271 #ifdef __BIG_ENDIAN_BITFIELD
273  uint64_t wlb_msk:4;
275  uint64_t dtcnt:9;
276  uint64_t dt:1;
278  uint64_t wlb_dat:4;
279 #else
287 #endif
288  } cn30xx;
290 #ifdef __BIG_ENDIAN_BITFIELD
292  uint64_t wlb_msk:4;
294  uint64_t dtcnt:10;
295  uint64_t dt:1;
296  uint64_t stin_msk:1;
297  uint64_t wlb_dat:4;
298 #else
306 #endif
307  } cn31xx;
309 #ifdef __BIG_ENDIAN_BITFIELD
311  uint64_t dtcnt:13;
312  uint64_t dt:1;
313  uint64_t stin_msk:1;
314  uint64_t wlb_dat:4;
315 #else
321 #endif
322  } cn38xx;
325 #ifdef __BIG_ENDIAN_BITFIELD
327  uint64_t dtbnk:1;
328  uint64_t wlb_msk:4;
330  uint64_t dtcnt:10;
331  uint64_t dt:1;
332  uint64_t stin_msk:1;
333  uint64_t wlb_dat:4;
334 #else
343 #endif
344  } cn50xx;
351 };
352 
356 #ifdef __BIG_ENDIAN_BITFIELD
358  uint64_t l2t:9;
359 #else
362 #endif
363  } s;
365 #ifdef __BIG_ENDIAN_BITFIELD
367  uint64_t vwdf:4;
368  uint64_t lrf:2;
369  uint64_t vab_vwcf:1;
371  uint64_t l2t:5;
372 #else
379 #endif
380  } cn30xx;
383 #ifdef __BIG_ENDIAN_BITFIELD
385  uint64_t vwdf:4;
386  uint64_t lrf:2;
387  uint64_t vab_vwcf:1;
388  uint64_t l2t:9;
389 #else
395 #endif
396  } cn38xx;
400 #ifdef __BIG_ENDIAN_BITFIELD
402  uint64_t plc2:1;
403  uint64_t plc1:1;
404  uint64_t plc0:1;
405  uint64_t vwdf:4;
407  uint64_t ilc:1;
408  uint64_t vab_vwcf:1;
409  uint64_t l2t:9;
410 #else
420 #endif
421  } cn52xx;
424 #ifdef __BIG_ENDIAN_BITFIELD
426  uint64_t plc2:1;
427  uint64_t plc1:1;
428  uint64_t plc0:1;
429  uint64_t ilc:1;
430  uint64_t vwdf1:4;
431  uint64_t vwdf0:4;
435  uint64_t l2t:9;
436 #else
448 #endif
449  } cn56xx;
453 };
454 
458 #ifdef __BIG_ENDIAN_BITFIELD
460  uint64_t mrb:4;
462  uint64_t ipcbst:1;
463  uint64_t picbst:1;
464  uint64_t xrdmsk:1;
465  uint64_t xrddat:1;
466 #else
474 #endif
475  } s;
477 #ifdef __BIG_ENDIAN_BITFIELD
479  uint64_t mrb:4;
480  uint64_t rmdf:4;
482  uint64_t ipcbst:1;
484  uint64_t xrdmsk:1;
485  uint64_t xrddat:1;
486 #else
495 #endif
496  } cn30xx;
499 #ifdef __BIG_ENDIAN_BITFIELD
501  uint64_t mrb:4;
502  uint64_t rmdf:4;
503  uint64_t rhdf:4;
504  uint64_t ipcbst:1;
505  uint64_t picbst:1;
506  uint64_t xrdmsk:1;
507  uint64_t xrddat:1;
508 #else
517 #endif
518  } cn38xx;
524 #ifdef __BIG_ENDIAN_BITFIELD
526  uint64_t mrb:4;
527  uint64_t rmdb:4;
528  uint64_t rhdb:4;
529  uint64_t ipcbst:1;
530  uint64_t picbst:1;
531  uint64_t xrdmsk:1;
532  uint64_t xrddat:1;
533 #else
542 #endif
543  } cn56xx;
547 };
548 
552 #ifdef __BIG_ENDIAN_BITFIELD
556  uint64_t rdffl:1;
557  uint64_t vbffl:4;
558 #else
564 #endif
565  } s;
573 };
574 
578 #ifdef __BIG_ENDIAN_BITFIELD
580  uint64_t fbfrspfl:8;
581  uint64_t sbffl:8;
582  uint64_t fbffl:8;
583  uint64_t l2dfl:8;
584 #else
590 #endif
591  } s;
595 #ifdef __BIG_ENDIAN_BITFIELD
597  uint64_t sbffl:8;
598  uint64_t fbffl:8;
599  uint64_t l2dfl:8;
600 #else
605 #endif
606  } cn63xxp1;
611 };
612 
616 #ifdef __BIG_ENDIAN_BITFIELD
618  uint64_t lrufl:1;
619  uint64_t tagfl:16;
620 #else
624 #endif
625  } s;
633 };
634 
637  struct cvmx_l2c_cfg_s {
638 #ifdef __BIG_ENDIAN_BITFIELD
640  uint64_t bstrun:1;
641  uint64_t lbist:1;
642  uint64_t xor_bank:1;
643  uint64_t dpres1:1;
644  uint64_t dpres0:1;
646  uint64_t fpexp:4;
647  uint64_t fpempty:1;
648  uint64_t fpen:1;
649  uint64_t idxalias:1;
650  uint64_t mwf_crd:4;
654 #else
670 #endif
671  } s;
673 #ifdef __BIG_ENDIAN_BITFIELD
675  uint64_t fpexp:4;
676  uint64_t fpempty:1;
677  uint64_t fpen:1;
678  uint64_t idxalias:1;
679  uint64_t mwf_crd:4;
683 #else
693 #endif
694  } cn30xx;
699 #ifdef __BIG_ENDIAN_BITFIELD
701  uint64_t bstrun:1;
702  uint64_t lbist:1;
704  uint64_t fpexp:4;
705  uint64_t fpempty:1;
706  uint64_t fpen:1;
707  uint64_t idxalias:1;
708  uint64_t mwf_crd:4;
712 #else
725 #endif
726  } cn50xx;
732 #ifdef __BIG_ENDIAN_BITFIELD
734  uint64_t bstrun:1;
735  uint64_t lbist:1;
738  uint64_t fpexp:4;
739  uint64_t fpempty:1;
740  uint64_t fpen:1;
741  uint64_t idxalias:1;
742  uint64_t mwf_crd:4;
746 #else
760 #endif
761  } cn58xx;
763 #ifdef __BIG_ENDIAN_BITFIELD
766  uint64_t fpexp:4;
767  uint64_t fpempty:1;
768  uint64_t fpen:1;
769  uint64_t idxalias:1;
770  uint64_t mwf_crd:4;
774 #else
785 #endif
786  } cn58xxp1;
787 };
788 
792 #ifdef __BIG_ENDIAN_BITFIELD
793  uint64_t data:64;
794 #else
796 #endif
797  } s;
805 };
806 
809  struct cvmx_l2c_ctl_s {
810 #ifdef __BIG_ENDIAN_BITFIELD
812  uint64_t sepcmt:1;
813  uint64_t rdf_fast:1;
815  uint64_t l2dfsbe:1;
816  uint64_t l2dfdbe:1;
817  uint64_t discclk:1;
818  uint64_t maxvab:4;
819  uint64_t maxlfb:4;
822  uint64_t ef_ena:1;
823  uint64_t ef_cnt:7;
825  uint64_t disecc:1;
827 #else
844 #endif
845  } s;
847 #ifdef __BIG_ENDIAN_BITFIELD
849  uint64_t rdf_fast:1;
851  uint64_t l2dfsbe:1;
852  uint64_t l2dfdbe:1;
853  uint64_t discclk:1;
854  uint64_t maxvab:4;
855  uint64_t maxlfb:4;
858  uint64_t ef_ena:1;
859  uint64_t ef_cnt:7;
861  uint64_t disecc:1;
863 #else
879 #endif
880  } cn61xx;
882 #ifdef __BIG_ENDIAN_BITFIELD
885  uint64_t l2dfsbe:1;
886  uint64_t l2dfdbe:1;
887  uint64_t discclk:1;
888  uint64_t maxvab:4;
889  uint64_t maxlfb:4;
892  uint64_t ef_ena:1;
893  uint64_t ef_cnt:7;
895  uint64_t disecc:1;
897 #else
912 #endif
913  } cn63xx;
915 #ifdef __BIG_ENDIAN_BITFIELD
917  uint64_t discclk:1;
918  uint64_t maxvab:4;
919  uint64_t maxlfb:4;
922  uint64_t ef_ena:1;
923  uint64_t ef_cnt:7;
925  uint64_t disecc:1;
927 #else
939 #endif
940  } cn63xxp1;
945 };
946 
949  struct cvmx_l2c_dbg_s {
950 #ifdef __BIG_ENDIAN_BITFIELD
952  uint64_t lfb_enum:4;
953  uint64_t lfb_dmp:1;
954  uint64_t ppnum:4;
955  uint64_t set:3;
956  uint64_t finv:1;
957  uint64_t l2d:1;
958  uint64_t l2t:1;
959 #else
963  uint64_t set:3;
968 #endif
969  } s;
971 #ifdef __BIG_ENDIAN_BITFIELD
973  uint64_t lfb_enum:2;
974  uint64_t lfb_dmp:1;
976  uint64_t ppnum:1;
978  uint64_t set:2;
979  uint64_t finv:1;
980  uint64_t l2d:1;
981  uint64_t l2t:1;
982 #else
986  uint64_t set:2;
993 #endif
994  } cn30xx;
996 #ifdef __BIG_ENDIAN_BITFIELD
998  uint64_t lfb_enum:3;
999  uint64_t lfb_dmp:1;
1001  uint64_t ppnum:1;
1003  uint64_t set:2;
1004  uint64_t finv:1;
1005  uint64_t l2d:1;
1006  uint64_t l2t:1;
1007 #else
1011  uint64_t set:2;
1018 #endif
1019  } cn31xx;
1023 #ifdef __BIG_ENDIAN_BITFIELD
1025  uint64_t lfb_enum:3;
1026  uint64_t lfb_dmp:1;
1028  uint64_t ppnum:1;
1029  uint64_t set:3;
1030  uint64_t finv:1;
1031  uint64_t l2d:1;
1032  uint64_t l2t:1;
1033 #else
1037  uint64_t set:3;
1043 #endif
1044  } cn50xx;
1046 #ifdef __BIG_ENDIAN_BITFIELD
1048  uint64_t lfb_enum:3;
1049  uint64_t lfb_dmp:1;
1051  uint64_t ppnum:2;
1052  uint64_t set:3;
1053  uint64_t finv:1;
1054  uint64_t l2d:1;
1055  uint64_t l2t:1;
1056 #else
1060  uint64_t set:3;
1066 #endif
1067  } cn52xx;
1073 };
1074 
1078 #ifdef __BIG_ENDIAN_BITFIELD
1080  uint64_t dtena:1;
1082  uint64_t dt_vld:1;
1083  uint64_t dt_tag:29;
1084 #else
1090 #endif
1091  } s;
1103 };
1104 
1108 #ifdef __BIG_ENDIAN_BITFIELD
1110  uint64_t tag:28;
1112  uint64_t valid:1;
1113 #else
1118 #endif
1119  } s;
1127 };
1128 
1132 #ifdef __BIG_ENDIAN_BITFIELD
1133  uint64_t dbe:1;
1134  uint64_t sbe:1;
1135  uint64_t vdbe:1;
1136  uint64_t vsbe:1;
1137  uint64_t syn:10;
1139  uint64_t wayidx:18;
1141  uint64_t type:2;
1142 #else
1152 #endif
1153  } s;
1155 #ifdef __BIG_ENDIAN_BITFIELD
1156  uint64_t dbe:1;
1157  uint64_t sbe:1;
1158  uint64_t vdbe:1;
1159  uint64_t vsbe:1;
1160  uint64_t syn:10;
1162  uint64_t wayidx:16;
1164  uint64_t type:2;
1165 #else
1175 #endif
1176  } cn61xx;
1178 #ifdef __BIG_ENDIAN_BITFIELD
1179  uint64_t dbe:1;
1180  uint64_t sbe:1;
1181  uint64_t vdbe:1;
1182  uint64_t vsbe:1;
1183  uint64_t syn:10;
1185  uint64_t wayidx:17;
1187  uint64_t type:2;
1188 #else
1198 #endif
1199  } cn63xx;
1205 };
1206 
1210 #ifdef __BIG_ENDIAN_BITFIELD
1211  uint64_t dbe:1;
1212  uint64_t sbe:1;
1213  uint64_t noway:1;
1215  uint64_t syn:6;
1217  uint64_t wayidx:15;
1219  uint64_t type:2;
1220 #else
1230 #endif
1231  } s;
1233 #ifdef __BIG_ENDIAN_BITFIELD
1234  uint64_t dbe:1;
1235  uint64_t sbe:1;
1236  uint64_t noway:1;
1238  uint64_t syn:6;
1240  uint64_t wayidx:13;
1242  uint64_t type:2;
1243 #else
1253 #endif
1254  } cn61xx;
1256 #ifdef __BIG_ENDIAN_BITFIELD
1257  uint64_t dbe:1;
1258  uint64_t sbe:1;
1259  uint64_t noway:1;
1261  uint64_t syn:6;
1263  uint64_t wayidx:14;
1265  uint64_t type:2;
1266 #else
1276 #endif
1277  } cn63xx;
1283 };
1284 
1288 #ifdef __BIG_ENDIAN_BITFIELD
1290  uint64_t vdbe:1;
1291  uint64_t vsbe:1;
1292  uint64_t vsyn:10;
1294  uint64_t type:2;
1295 #else
1302 #endif
1303  } s;
1311 };
1312 
1316 #ifdef __BIG_ENDIAN_BITFIELD
1317  uint64_t cmd:6;
1319  uint64_t sid:6;
1321  uint64_t addr:38;
1322 #else
1328 #endif
1329  } s;
1331 #ifdef __BIG_ENDIAN_BITFIELD
1332  uint64_t cmd:6;
1334  uint64_t sid:4;
1336  uint64_t addr:38;
1337 #else
1343 #endif
1344  } cn61xx;
1348 #ifdef __BIG_ENDIAN_BITFIELD
1349  uint64_t cmd:6;
1351  uint64_t sid:5;
1353  uint64_t addr:38;
1354 #else
1360 #endif
1361  } cn66xx;
1365 };
1366 
1370 #ifdef __BIG_ENDIAN_BITFIELD
1371  uint64_t plc1rmsk:32;
1372  uint64_t plc0rmsk:32;
1373 #else
1376 #endif
1377  } s;
1382 };
1383 
1387 #ifdef __BIG_ENDIAN_BITFIELD
1388  uint64_t ilcrmsk:32;
1389  uint64_t plc2rmsk:32;
1390 #else
1393 #endif
1394  } s;
1399 };
1400 
1404 #ifdef __BIG_ENDIAN_BITFIELD
1406  uint64_t lck2ena:1;
1407  uint64_t lckena:1;
1408  uint64_t l2ddeden:1;
1409  uint64_t l2dsecen:1;
1410  uint64_t l2tdeden:1;
1411  uint64_t l2tsecen:1;
1412  uint64_t oob3en:1;
1413  uint64_t oob2en:1;
1414  uint64_t oob1en:1;
1415 #else
1426 #endif
1427  } s;
1432 };
1433 
1437 #ifdef __BIG_ENDIAN_BITFIELD
1439  uint64_t bigrd:1;
1440  uint64_t bigwr:1;
1441  uint64_t vrtpe:1;
1442  uint64_t vrtadrng:1;
1443  uint64_t vrtidrng:1;
1444  uint64_t vrtwr:1;
1445  uint64_t holewr:1;
1446  uint64_t holerd:1;
1447 #else
1457 #endif
1458  } s;
1462 #ifdef __BIG_ENDIAN_BITFIELD
1464  uint64_t vrtpe:1;
1465  uint64_t vrtadrng:1;
1466  uint64_t vrtidrng:1;
1467  uint64_t vrtwr:1;
1468  uint64_t holewr:1;
1469  uint64_t holerd:1;
1470 #else
1478 #endif
1479  } cn63xxp1;
1484 };
1485 
1489 #ifdef __BIG_ENDIAN_BITFIELD
1491  uint64_t tad3:1;
1492  uint64_t tad2:1;
1493  uint64_t tad1:1;
1494  uint64_t tad0:1;
1496  uint64_t bigrd:1;
1497  uint64_t bigwr:1;
1498  uint64_t vrtpe:1;
1499  uint64_t vrtadrng:1;
1500  uint64_t vrtidrng:1;
1501  uint64_t vrtwr:1;
1502  uint64_t holewr:1;
1503  uint64_t holerd:1;
1504 #else
1519 #endif
1520  } s;
1522 #ifdef __BIG_ENDIAN_BITFIELD
1524  uint64_t tad0:1;
1526  uint64_t bigrd:1;
1527  uint64_t bigwr:1;
1528  uint64_t vrtpe:1;
1529  uint64_t vrtadrng:1;
1530  uint64_t vrtidrng:1;
1531  uint64_t vrtwr:1;
1532  uint64_t holewr:1;
1533  uint64_t holerd:1;
1534 #else
1546 #endif
1547  } cn61xx;
1550 #ifdef __BIG_ENDIAN_BITFIELD
1552  uint64_t tad0:1;
1554  uint64_t vrtpe:1;
1555  uint64_t vrtadrng:1;
1556  uint64_t vrtidrng:1;
1557  uint64_t vrtwr:1;
1558  uint64_t holewr:1;
1559  uint64_t holerd:1;
1560 #else
1570 #endif
1571  } cn63xxp1;
1576 };
1577 
1581 #ifdef __BIG_ENDIAN_BITFIELD
1583  uint64_t lck2:1;
1584  uint64_t lck:1;
1585  uint64_t l2dded:1;
1586  uint64_t l2dsec:1;
1587  uint64_t l2tded:1;
1588  uint64_t l2tsec:1;
1589  uint64_t oob3:1;
1590  uint64_t oob2:1;
1591  uint64_t oob1:1;
1592 #else
1603 #endif
1604  } s;
1609 };
1610 
1614 #ifdef __BIG_ENDIAN_BITFIELD
1615  uint64_t count:64;
1616 #else
1618 #endif
1619  } s;
1627 };
1628 
1632 #ifdef __BIG_ENDIAN_BITFIELD
1633  uint64_t count:64;
1634 #else
1636 #endif
1637  } s;
1645 };
1646 
1650 #ifdef __BIG_ENDIAN_BITFIELD
1652  uint64_t lck_base:27;
1654  uint64_t lck_ena:1;
1655 #else
1660 #endif
1661  } s;
1673 };
1674 
1678 #ifdef __BIG_ENDIAN_BITFIELD
1680  uint64_t lck_offset:10;
1681 #else
1684 #endif
1685  } s;
1697 };
1698 
1702 #ifdef __BIG_ENDIAN_BITFIELD
1704  uint64_t stcpnd:1;
1705  uint64_t stpnd:1;
1706  uint64_t stinv:1;
1707  uint64_t stcfl:1;
1708  uint64_t vam:1;
1709  uint64_t inxt:4;
1710  uint64_t itl:1;
1711  uint64_t ihd:1;
1712  uint64_t set:3;
1713  uint64_t vabnum:4;
1714  uint64_t sid:9;
1715  uint64_t cmd:4;
1716  uint64_t vld:1;
1717 #else
1722  uint64_t set:3;
1732 #endif
1733  } s;
1735 #ifdef __BIG_ENDIAN_BITFIELD
1737  uint64_t stcpnd:1;
1738  uint64_t stpnd:1;
1739  uint64_t stinv:1;
1740  uint64_t stcfl:1;
1741  uint64_t vam:1;
1743  uint64_t inxt:2;
1744  uint64_t itl:1;
1745  uint64_t ihd:1;
1747  uint64_t set:2;
1749  uint64_t vabnum:2;
1750  uint64_t sid:9;
1751  uint64_t cmd:4;
1752  uint64_t vld:1;
1753 #else
1759  uint64_t set:2;
1771 #endif
1772  } cn30xx;
1774 #ifdef __BIG_ENDIAN_BITFIELD
1776  uint64_t stcpnd:1;
1777  uint64_t stpnd:1;
1778  uint64_t stinv:1;
1779  uint64_t stcfl:1;
1780  uint64_t vam:1;
1782  uint64_t inxt:3;
1783  uint64_t itl:1;
1784  uint64_t ihd:1;
1786  uint64_t set:2;
1788  uint64_t vabnum:3;
1789  uint64_t sid:9;
1790  uint64_t cmd:4;
1791  uint64_t vld:1;
1792 #else
1798  uint64_t set:2;
1810 #endif
1811  } cn31xx;
1815 #ifdef __BIG_ENDIAN_BITFIELD
1817  uint64_t stcpnd:1;
1818  uint64_t stpnd:1;
1819  uint64_t stinv:1;
1820  uint64_t stcfl:1;
1821  uint64_t vam:1;
1823  uint64_t inxt:3;
1824  uint64_t itl:1;
1825  uint64_t ihd:1;
1826  uint64_t set:3;
1828  uint64_t vabnum:3;
1829  uint64_t sid:9;
1830  uint64_t cmd:4;
1831  uint64_t vld:1;
1832 #else
1838  uint64_t set:3;
1849 #endif
1850  } cn50xx;
1857 };
1858 
1862 #ifdef __BIG_ENDIAN_BITFIELD
1864  uint64_t dsgoing:1;
1865  uint64_t bid:2;
1866  uint64_t wtrsp:1;
1867  uint64_t wtdw:1;
1868  uint64_t wtdq:1;
1869  uint64_t wtwhp:1;
1870  uint64_t wtwhf:1;
1871  uint64_t wtwrm:1;
1872  uint64_t wtstm:1;
1873  uint64_t wtrda:1;
1874  uint64_t wtstdt:1;
1875  uint64_t wtstrsp:1;
1876  uint64_t wtstrsc:1;
1877  uint64_t wtvtm:1;
1878  uint64_t wtmfl:1;
1879  uint64_t prbrty:1;
1880  uint64_t wtprb:1;
1881  uint64_t vld:1;
1882 #else
1902 #endif
1903  } s;
1915 };
1916 
1920 #ifdef __BIG_ENDIAN_BITFIELD
1922 #else
1924 #endif
1925  } s;
1927 #ifdef __BIG_ENDIAN_BITFIELD
1929  uint64_t lfb_tag:19;
1930  uint64_t lfb_idx:8;
1931 #else
1935 #endif
1936  } cn30xx;
1938 #ifdef __BIG_ENDIAN_BITFIELD
1940  uint64_t lfb_tag:17;
1941  uint64_t lfb_idx:10;
1942 #else
1946 #endif
1947  } cn31xx;
1951 #ifdef __BIG_ENDIAN_BITFIELD
1953  uint64_t lfb_tag:20;
1954  uint64_t lfb_idx:7;
1955 #else
1959 #endif
1960  } cn50xx;
1962 #ifdef __BIG_ENDIAN_BITFIELD
1964  uint64_t lfb_tag:18;
1965  uint64_t lfb_idx:9;
1966 #else
1970 #endif
1971  } cn52xx;
1974 #ifdef __BIG_ENDIAN_BITFIELD
1976  uint64_t lfb_tag:16;
1977  uint64_t lfb_idx:11;
1978 #else
1982 #endif
1983  } cn56xx;
1987 };
1988 
1992 #ifdef __BIG_ENDIAN_BITFIELD
1994  uint64_t stpartdis:1;
1995  uint64_t lfb_hwm:4;
1996 #else
2000 #endif
2001  } s;
2003 #ifdef __BIG_ENDIAN_BITFIELD
2005  uint64_t stpartdis:1;
2007  uint64_t lfb_hwm:2;
2008 #else
2013 #endif
2014  } cn30xx;
2016 #ifdef __BIG_ENDIAN_BITFIELD
2018  uint64_t stpartdis:1;
2020  uint64_t lfb_hwm:3;
2021 #else
2026 #endif
2027  } cn31xx;
2037 };
2038 
2042 #ifdef __BIG_ENDIAN_BITFIELD
2044  uint64_t dwbena:1;
2045  uint64_t stena:1;
2046 #else
2050 #endif
2051  } s;
2056 };
2057 
2061 #ifdef __BIG_ENDIAN_BITFIELD
2062  uint64_t fadr:27;
2063  uint64_t fsrc:1;
2065  uint64_t sadr:14;
2067  uint64_t size:14;
2068 #else
2075 #endif
2076  } s;
2081 };
2082 
2086 #ifdef __BIG_ENDIAN_BITFIELD
2087  uint64_t fadr:27;
2088  uint64_t fsrc:1;
2090  uint64_t sadr:14;
2092  uint64_t size:14;
2093 #else
2100 #endif
2101  } s;
2106 };
2107 
2111 #ifdef __BIG_ENDIAN_BITFIELD
2112  uint64_t fadr:27;
2113  uint64_t fsrc:1;
2115  uint64_t sadr:14;
2117  uint64_t size:14;
2118 #else
2125 #endif
2126  } s;
2131 };
2132 
2136 #ifdef __BIG_ENDIAN_BITFIELD
2138  uint64_t pfcnt0:36;
2139 #else
2142 #endif
2143  } s;
2155 };
2156 
2160 #ifdef __BIG_ENDIAN_BITFIELD
2162  uint64_t cnt3rdclr:1;
2163  uint64_t cnt2rdclr:1;
2164  uint64_t cnt1rdclr:1;
2165  uint64_t cnt0rdclr:1;
2166  uint64_t cnt3ena:1;
2167  uint64_t cnt3clr:1;
2168  uint64_t cnt3sel:6;
2169  uint64_t cnt2ena:1;
2170  uint64_t cnt2clr:1;
2171  uint64_t cnt2sel:6;
2172  uint64_t cnt1ena:1;
2173  uint64_t cnt1clr:1;
2174  uint64_t cnt1sel:6;
2175  uint64_t cnt0ena:1;
2176  uint64_t cnt0clr:1;
2177  uint64_t cnt0sel:6;
2178 #else
2196 #endif
2197  } s;
2209 };
2210 
2214 #ifdef __BIG_ENDIAN_BITFIELD
2216  uint64_t pp11grp:2;
2217  uint64_t pp10grp:2;
2218  uint64_t pp9grp:2;
2219  uint64_t pp8grp:2;
2220  uint64_t pp7grp:2;
2221  uint64_t pp6grp:2;
2222  uint64_t pp5grp:2;
2223  uint64_t pp4grp:2;
2224  uint64_t pp3grp:2;
2225  uint64_t pp2grp:2;
2226  uint64_t pp1grp:2;
2227  uint64_t pp0grp:2;
2228 #else
2242 #endif
2243  } s;
2245 #ifdef __BIG_ENDIAN_BITFIELD
2247  uint64_t pp3grp:2;
2248  uint64_t pp2grp:2;
2249  uint64_t pp1grp:2;
2250  uint64_t pp0grp:2;
2251 #else
2257 #endif
2258  } cn52xx;
2262 };
2263 
2267 #ifdef __BIG_ENDIAN_BITFIELD
2269  uint64_t dwblvl:3;
2271  uint64_t lvl:3;
2272 #else
2277 #endif
2278  } s;
2280 #ifdef __BIG_ENDIAN_BITFIELD
2282  uint64_t dwblvl:2;
2284  uint64_t lvl:2;
2285 #else
2290 #endif
2291  } cn61xx;
2298 };
2299 
2303 #ifdef __BIG_ENDIAN_BITFIELD
2305  uint64_t lvl:3;
2306 #else
2309 #endif
2310  } s;
2312 #ifdef __BIG_ENDIAN_BITFIELD
2314  uint64_t lvl:2;
2315 #else
2318 #endif
2319  } cn61xx;
2326 };
2327 
2331 #ifdef __BIG_ENDIAN_BITFIELD
2332  uint64_t wgt7:8;
2333  uint64_t wgt6:8;
2334  uint64_t wgt5:8;
2335  uint64_t wgt4:8;
2336  uint64_t wgt3:8;
2337  uint64_t wgt2:8;
2338  uint64_t wgt1:8;
2339  uint64_t wgt0:8;
2340 #else
2349 #endif
2350  } s;
2352 #ifdef __BIG_ENDIAN_BITFIELD
2354  uint64_t wgt3:8;
2355  uint64_t wgt2:8;
2356  uint64_t wgt1:8;
2357  uint64_t wgt0:8;
2358 #else
2364 #endif
2365  } cn61xx;
2372 };
2373 
2377 #ifdef __BIG_ENDIAN_BITFIELD
2378  uint64_t count:64;
2379 #else
2381 #endif
2382  } s;
2390 };
2391 
2395 #ifdef __BIG_ENDIAN_BITFIELD
2396  uint64_t count:64;
2397 #else
2399 #endif
2400  } s;
2408 };
2409 
2413 #ifdef __BIG_ENDIAN_BITFIELD
2415  uint64_t umsk3:8;
2416  uint64_t umsk2:8;
2417  uint64_t umsk1:8;
2418  uint64_t umsk0:8;
2419 #else
2425 #endif
2426  } s;
2428 #ifdef __BIG_ENDIAN_BITFIELD
2430  uint64_t umsk0:4;
2431 #else
2434 #endif
2435  } cn30xx;
2437 #ifdef __BIG_ENDIAN_BITFIELD
2439  uint64_t umsk1:4;
2441  uint64_t umsk0:4;
2442 #else
2447 #endif
2448  } cn31xx;
2452 #ifdef __BIG_ENDIAN_BITFIELD
2454  uint64_t umsk1:8;
2455  uint64_t umsk0:8;
2456 #else
2460 #endif
2461  } cn50xx;
2468 };
2469 
2473 #ifdef __BIG_ENDIAN_BITFIELD
2475  uint64_t umsk7:8;
2476  uint64_t umsk6:8;
2477  uint64_t umsk5:8;
2478  uint64_t umsk4:8;
2479 #else
2485 #endif
2486  } s;
2493 };
2494 
2498 #ifdef __BIG_ENDIAN_BITFIELD
2500  uint64_t umsk11:8;
2501  uint64_t umsk10:8;
2502  uint64_t umsk9:8;
2503  uint64_t umsk8:8;
2504 #else
2510 #endif
2511  } s;
2518 };
2519 
2523 #ifdef __BIG_ENDIAN_BITFIELD
2525  uint64_t umsk15:8;
2526  uint64_t umsk14:8;
2527  uint64_t umsk13:8;
2528  uint64_t umsk12:8;
2529 #else
2535 #endif
2536  } s;
2541 };
2542 
2546 #ifdef __BIG_ENDIAN_BITFIELD
2548  uint64_t umskiob:8;
2549 #else
2552 #endif
2553  } s;
2555 #ifdef __BIG_ENDIAN_BITFIELD
2557  uint64_t umskiob:4;
2558 #else
2561 #endif
2562  } cn30xx;
2573 };
2574 
2578 #ifdef __BIG_ENDIAN_BITFIELD
2580  uint64_t ow3ecc:10;
2582  uint64_t ow2ecc:10;
2584  uint64_t ow1ecc:10;
2586  uint64_t ow0ecc:10;
2587 #else
2596 #endif
2597  } s;
2605 };
2606 
2610 #ifdef __BIG_ENDIAN_BITFIELD
2612  uint64_t ow7ecc:10;
2614  uint64_t ow6ecc:10;
2616  uint64_t ow5ecc:10;
2618  uint64_t ow4ecc:10;
2619 #else
2628 #endif
2629  } s;
2637 };
2638 
2642 #ifdef __BIG_ENDIAN_BITFIELD
2644  uint64_t wrdislmc:1;
2645  uint64_t rddislmc:1;
2646  uint64_t noway:1;
2647  uint64_t vbfdbe:1;
2648  uint64_t vbfsbe:1;
2649  uint64_t tagdbe:1;
2650  uint64_t tagsbe:1;
2651  uint64_t l2ddbe:1;
2652  uint64_t l2dsbe:1;
2653 #else
2664 #endif
2665  } s;
2669 #ifdef __BIG_ENDIAN_BITFIELD
2671  uint64_t noway:1;
2672  uint64_t vbfdbe:1;
2673  uint64_t vbfsbe:1;
2674  uint64_t tagdbe:1;
2675  uint64_t tagsbe:1;
2676  uint64_t l2ddbe:1;
2677  uint64_t l2dsbe:1;
2678 #else
2687 #endif
2688  } cn63xxp1;
2693 };
2694 
2698 #ifdef __BIG_ENDIAN_BITFIELD
2700  uint64_t wrdislmc:1;
2701  uint64_t rddislmc:1;
2702  uint64_t noway:1;
2703  uint64_t vbfdbe:1;
2704  uint64_t vbfsbe:1;
2705  uint64_t tagdbe:1;
2706  uint64_t tagsbe:1;
2707  uint64_t l2ddbe:1;
2708  uint64_t l2dsbe:1;
2709 #else
2720 #endif
2721  } s;
2728 };
2729 
2733 #ifdef __BIG_ENDIAN_BITFIELD
2734  uint64_t count:64;
2735 #else
2737 #endif
2738  } s;
2746 };
2747 
2751 #ifdef __BIG_ENDIAN_BITFIELD
2752  uint64_t count:64;
2753 #else
2755 #endif
2756  } s;
2764 };
2765 
2769 #ifdef __BIG_ENDIAN_BITFIELD
2770  uint64_t count:64;
2771 #else
2773 #endif
2774  } s;
2782 };
2783 
2787 #ifdef __BIG_ENDIAN_BITFIELD
2788  uint64_t count:64;
2789 #else
2791 #endif
2792  } s;
2800 };
2801 
2805 #ifdef __BIG_ENDIAN_BITFIELD
2807  uint64_t cnt3sel:8;
2808  uint64_t cnt2sel:8;
2809  uint64_t cnt1sel:8;
2810  uint64_t cnt0sel:8;
2811 #else
2817 #endif
2818  } s;
2826 };
2827 
2831 #ifdef __BIG_ENDIAN_BITFIELD
2833  uint64_t ecc:6;
2835  uint64_t tag:19;
2837  uint64_t use:1;
2838  uint64_t valid:1;
2839  uint64_t dirty:1;
2840  uint64_t lock:1;
2841 #else
2851 #endif
2852  } s;
2860 };
2861 
2865 #ifdef __BIG_ENDIAN_BITFIELD
2866  uint64_t mask:64;
2867 #else
2869 #endif
2870  } s;
2878 };
2879 
2883 #ifdef __BIG_ENDIAN_BITFIELD
2885  uint64_t mask:2;
2886 #else
2889 #endif
2890  } s;
2892 #ifdef __BIG_ENDIAN_BITFIELD
2894  uint64_t mask:1;
2895 #else
2898 #endif
2899  } cn61xx;
2906 };
2907 
2911 #ifdef __BIG_ENDIAN_BITFIELD
2913  uint64_t invl2:1;
2914  uint64_t dwb:1;
2915 #else
2919 #endif
2920  } s;
2927 };
2928 
2932 #ifdef __BIG_ENDIAN_BITFIELD
2934  uint64_t mask:32;
2935 #else
2938 #endif
2939  } s;
2941 #ifdef __BIG_ENDIAN_BITFIELD
2943  uint64_t mask:4;
2944 #else
2947 #endif
2948  } cn61xx;
2950 #ifdef __BIG_ENDIAN_BITFIELD
2952  uint64_t mask:6;
2953 #else
2956 #endif
2957  } cn63xx;
2960 #ifdef __BIG_ENDIAN_BITFIELD
2962  uint64_t mask:10;
2963 #else
2966 #endif
2967  } cn66xx;
2971 };
2972 
2976 #ifdef __BIG_ENDIAN_BITFIELD
2978  uint64_t dwbid:6;
2980  uint64_t id:6;
2981 #else
2982  uint64_t id:6;
2986 #endif
2987  } s;
2995 };
2996 
3000 #ifdef __BIG_ENDIAN_BITFIELD
3002  uint64_t id:6;
3003 #else
3004  uint64_t id:6;
3006 #endif
3007  } s;
3015 };
3016 
3020 #ifdef __BIG_ENDIAN_BITFIELD
3022  uint64_t ooberr:1;
3024  uint64_t memsz:3;
3025  uint64_t numid:3;
3026  uint64_t enable:1;
3027 #else
3034 #endif
3035  } s;
3043 };
3044 
3048 #ifdef __BIG_ENDIAN_BITFIELD
3050  uint64_t parity:4;
3051  uint64_t data:32;
3052 #else
3056 #endif
3057  } s;
3065 };
3066 
3070 #ifdef __BIG_ENDIAN_BITFIELD
3072  uint64_t mask:16;
3073 #else
3076 #endif
3077  } s;
3085 };
3086 
3090 #ifdef __BIG_ENDIAN_BITFIELD
3092  uint64_t mask:16;
3093 #else
3096 #endif
3097  } s;
3105 };
3106 
3110 #ifdef __BIG_ENDIAN_BITFIELD
3111  uint64_t count:64;
3112 #else
3114 #endif
3115  } s;
3123 };
3124 
3128 #ifdef __BIG_ENDIAN_BITFIELD
3129  uint64_t inuse:1;
3130  uint64_t cmd:6;
3132  uint64_t addr:38;
3133 #else
3138 #endif
3139  } s;
3147 };
3148 
3152 #ifdef __BIG_ENDIAN_BITFIELD
3153  uint64_t count:64;
3154 #else
3156 #endif
3157  } s;
3165 };
3166 
3167 #endif