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cvmx-l2d-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
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17  * details.
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23  *
24  * This file may also be available under a different license from Cavium.
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26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_L2D_DEFS_H__
29 #define __CVMX_L2D_DEFS_H__
30 
31 #define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
32 #define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
33 #define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
34 #define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
35 #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
36 #define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
37 #define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
38 #define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
39 #define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
40 #define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
41 #define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
42 #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
43 
46  struct cvmx_l2d_bst0_s {
47 #ifdef __BIG_ENDIAN_BITFIELD
49  uint64_t ftl:1;
50  uint64_t q0stat:34;
51 #else
55 #endif
56  } s;
68 };
69 
72  struct cvmx_l2d_bst1_s {
73 #ifdef __BIG_ENDIAN_BITFIELD
75  uint64_t q1stat:34;
76 #else
79 #endif
80  } s;
92 };
93 
96  struct cvmx_l2d_bst2_s {
97 #ifdef __BIG_ENDIAN_BITFIELD
99  uint64_t q2stat:34;
100 #else
103 #endif
104  } s;
116 };
117 
121 #ifdef __BIG_ENDIAN_BITFIELD
123  uint64_t q3stat:34;
124 #else
127 #endif
128  } s;
140 };
141 
144  struct cvmx_l2d_err_s {
145 #ifdef __BIG_ENDIAN_BITFIELD
147  uint64_t bmhclsel:1;
148  uint64_t ded_err:1;
149  uint64_t sec_err:1;
152  uint64_t ecc_ena:1;
153 #else
161 #endif
162  } s;
174 };
175 
179 #ifdef __BIG_ENDIAN_BITFIELD
181  uint64_t fadru:1;
182  uint64_t fowmsk:4;
183  uint64_t fset:3;
184  uint64_t fadr:11;
185 #else
191 #endif
192  } s;
194 #ifdef __BIG_ENDIAN_BITFIELD
196  uint64_t fowmsk:4;
198  uint64_t fset:2;
200  uint64_t fadr:9;
201 #else
208 #endif
209  } cn30xx;
211 #ifdef __BIG_ENDIAN_BITFIELD
213  uint64_t fowmsk:4;
215  uint64_t fset:2;
217  uint64_t fadr:10;
218 #else
225 #endif
226  } cn31xx;
228 #ifdef __BIG_ENDIAN_BITFIELD
230  uint64_t fowmsk:4;
231  uint64_t fset:3;
232  uint64_t fadr:11;
233 #else
238 #endif
239  } cn38xx;
242 #ifdef __BIG_ENDIAN_BITFIELD
244  uint64_t fowmsk:4;
245  uint64_t fset:3;
247  uint64_t fadr:8;
248 #else
254 #endif
255  } cn50xx;
257 #ifdef __BIG_ENDIAN_BITFIELD
259  uint64_t fowmsk:4;
260  uint64_t fset:3;
262  uint64_t fadr:10;
263 #else
269 #endif
270  } cn52xx;
276 };
277 
281 #ifdef __BIG_ENDIAN_BITFIELD
283  uint64_t fsyn_ow1:10;
284  uint64_t fsyn_ow0:10;
285 #else
289 #endif
290  } s;
302 };
303 
307 #ifdef __BIG_ENDIAN_BITFIELD
309  uint64_t fsyn_ow3:10;
310  uint64_t fsyn_ow2:10;
311 #else
315 #endif
316  } s;
328 };
329 
333 #ifdef __BIG_ENDIAN_BITFIELD
335  uint64_t q0fus:34;
336 #else
339 #endif
340  } s;
352 };
353 
357 #ifdef __BIG_ENDIAN_BITFIELD
359  uint64_t q1fus:34;
360 #else
363 #endif
364  } s;
376 };
377 
381 #ifdef __BIG_ENDIAN_BITFIELD
383  uint64_t q2fus:34;
384 #else
387 #endif
388  } s;
400 };
401 
405 #ifdef __BIG_ENDIAN_BITFIELD
407  uint64_t ema_ctl:3;
409  uint64_t q3fus:34;
410 #else
415 #endif
416  } s;
418 #ifdef __BIG_ENDIAN_BITFIELD
420  uint64_t crip_64k:1;
421  uint64_t q3fus:34;
422 #else
426 #endif
427  } cn30xx;
429 #ifdef __BIG_ENDIAN_BITFIELD
432  uint64_t q3fus:34;
433 #else
437 #endif
438  } cn31xx;
440 #ifdef __BIG_ENDIAN_BITFIELD
444  uint64_t q3fus:34;
445 #else
450 #endif
451  } cn38xx;
454 #ifdef __BIG_ENDIAN_BITFIELD
456  uint64_t ema_ctl:3;
458  uint64_t crip_32k:1;
459  uint64_t crip_64k:1;
460  uint64_t q3fus:34;
461 #else
468 #endif
469  } cn50xx;
471 #ifdef __BIG_ENDIAN_BITFIELD
473  uint64_t ema_ctl:3;
477  uint64_t q3fus:34;
478 #else
485 #endif
486  } cn52xx;
489 #ifdef __BIG_ENDIAN_BITFIELD
491  uint64_t ema_ctl:3;
495  uint64_t q3fus:34;
496 #else
503 #endif
504  } cn56xx;
507 #ifdef __BIG_ENDIAN_BITFIELD
509  uint64_t ema_ctl:2;
513  uint64_t q3fus:34;
514 #else
521 #endif
522  } cn58xx;
524 };
525 
526 #endif