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cvmx-mixx-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
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15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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17  * details.
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23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_MIXX_DEFS_H__
29 #define __CVMX_MIXX_DEFS_H__
30 
31 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
32 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
33 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
34 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
35 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
36 #define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
37 #define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
38 #define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
39 #define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
40 #define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
41 #define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
42 #define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
43 #define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
44 #define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
45 #define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
46 
50 #ifdef __BIG_ENDIAN_BITFIELD
52  uint64_t opfdat:1;
53  uint64_t mrgdat:1;
54  uint64_t mrqdat:1;
55  uint64_t ipfdat:1;
56  uint64_t irfdat:1;
57  uint64_t orfdat:1;
58 #else
66 #endif
67  } s;
69 #ifdef __BIG_ENDIAN_BITFIELD
71  uint64_t mrqdat:1;
72  uint64_t ipfdat:1;
73  uint64_t irfdat:1;
74  uint64_t orfdat:1;
75 #else
81 #endif
82  } cn52xx;
92 };
93 
96  struct cvmx_mixx_ctl_s {
97 #ifdef __BIG_ENDIAN_BITFIELD
101  uint64_t busy:1;
102  uint64_t en:1;
103  uint64_t reset:1;
104  uint64_t lendian:1;
105  uint64_t nbtarb:1;
106  uint64_t mrq_hwm:2;
107 #else
117 #endif
118  } s;
120 #ifdef __BIG_ENDIAN_BITFIELD
123  uint64_t busy:1;
124  uint64_t en:1;
125  uint64_t reset:1;
126  uint64_t lendian:1;
127  uint64_t nbtarb:1;
128  uint64_t mrq_hwm:2;
129 #else
138 #endif
139  } cn52xx;
149 };
150 
154 #ifdef __BIG_ENDIAN_BITFIELD
156  uint64_t tsena:1;
157  uint64_t orunena:1;
158  uint64_t irunena:1;
160  uint64_t ithena:1;
161  uint64_t othena:1;
162  uint64_t ivfena:1;
163  uint64_t ovfena:1;
164 #else
174 #endif
175  } s;
177 #ifdef __BIG_ENDIAN_BITFIELD
179  uint64_t orunena:1;
180  uint64_t irunena:1;
182  uint64_t ithena:1;
183  uint64_t othena:1;
184  uint64_t ivfena:1;
185  uint64_t ovfena:1;
186 #else
195 #endif
196  } cn52xx;
206 };
207 
211 #ifdef __BIG_ENDIAN_BITFIELD
213  uint64_t ircnt:20;
214 #else
217 #endif
218  } s;
229 };
230 
234 #ifdef __BIG_ENDIAN_BITFIELD
236  uint64_t ibplwm:20;
237  uint64_t irhwm:20;
238 #else
242 #endif
243  } s;
254 };
255 
259 #ifdef __BIG_ENDIAN_BITFIELD
261  uint64_t isize:20;
262  uint64_t ibase:37;
264 #else
269 #endif
270  } s;
272 #ifdef __BIG_ENDIAN_BITFIELD
274  uint64_t isize:20;
276  uint64_t ibase:33;
278 #else
284 #endif
285  } cn52xx;
295 };
296 
300 #ifdef __BIG_ENDIAN_BITFIELD
302  uint64_t itlptr:20;
304  uint64_t idbell:20;
305 #else
310 #endif
311  } s;
322 };
323 
327 #ifdef __BIG_ENDIAN_BITFIELD
329  uint64_t ts:1;
330  uint64_t orun:1;
331  uint64_t irun:1;
332  uint64_t data_drp:1;
333  uint64_t irthresh:1;
334  uint64_t orthresh:1;
335  uint64_t idblovf:1;
336  uint64_t odblovf:1;
337 #else
347 #endif
348  } s;
350 #ifdef __BIG_ENDIAN_BITFIELD
352  uint64_t orun:1;
353  uint64_t irun:1;
354  uint64_t data_drp:1;
355  uint64_t irthresh:1;
356  uint64_t orthresh:1;
357  uint64_t idblovf:1;
358  uint64_t odblovf:1;
359 #else
368 #endif
369  } cn52xx;
379 };
380 
384 #ifdef __BIG_ENDIAN_BITFIELD
386  uint64_t orcnt:20;
387 #else
390 #endif
391  } s;
402 };
403 
407 #ifdef __BIG_ENDIAN_BITFIELD
409  uint64_t orhwm:20;
410 #else
413 #endif
414  } s;
425 };
426 
430 #ifdef __BIG_ENDIAN_BITFIELD
432  uint64_t osize:20;
433  uint64_t obase:37;
435 #else
440 #endif
441  } s;
443 #ifdef __BIG_ENDIAN_BITFIELD
445  uint64_t osize:20;
447  uint64_t obase:33;
449 #else
455 #endif
456  } cn52xx;
466 };
467 
471 #ifdef __BIG_ENDIAN_BITFIELD
473  uint64_t otlptr:20;
475  uint64_t odbell:20;
476 #else
481 #endif
482  } s;
493 };
494 
498 #ifdef __BIG_ENDIAN_BITFIELD
500  uint64_t iremcnt:20;
502  uint64_t oremcnt:20;
503 #else
508 #endif
509  } s;
520 };
521 
525 #ifdef __BIG_ENDIAN_BITFIELD
527  uint64_t tsavl:5;
529  uint64_t tstot:5;
531  uint64_t tscnt:5;
532 #else
539 #endif
540  } s;
547 };
548 
552 #ifdef __BIG_ENDIAN_BITFIELD
553  uint64_t tstamp:64;
554 #else
556 #endif
557  } s;
564 };
565 
566 #endif