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cvmx-pip-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT. See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_PIP_DEFS_H__
29 #define __CVMX_PIP_DEFS_H__
30 
31 /*
32  * Enumeration representing the amount of packet processing
33  * and validation performed by the input hardware.
34  */
36  /*
37  * Packet input doesn't perform any processing of the input
38  * packet.
39  */
41  /*
42  * Full packet processing is performed with pointer starting
43  * at the L2 (ethernet MAC) header.
44  */
46  /*
47  * Input packets are assumed to be IP. Results from non IP
48  * packets is undefined. Pointers reference the beginning of
49  * the IP header.
50  */
52 };
53 
54 #define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8)
55 #define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull))
56 #define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull))
57 #define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16)
58 #define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16)
59 #define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8)
60 #define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull))
61 #define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8)
62 #define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8)
63 #define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8)
64 #define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull))
65 #define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull))
66 #define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8)
67 #define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull))
68 #define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull))
69 #define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull))
70 #define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull))
71 #define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull))
72 #define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull))
73 #define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8)
74 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
75 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
76 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
77 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
78 #define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8)
79 #define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8)
80 #define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull))
81 #define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull))
82 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
83 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
84 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
85 #define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
86 #define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
87 #define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
88 #define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
89 #define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
90 #define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
91 #define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
92 #define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
93 #define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
94 #define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
95 #define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
96 #define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
97 #define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
98 #define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
99 #define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
100 #define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
101 #define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
102 #define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
103 #define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
104 #define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
105 #define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
106 #define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull))
107 #define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
108 #define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
109 #define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
110 #define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
111 #define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
112 #define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
113 #define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull))
114 #define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
115 #define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull))
116 #define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull))
117 #define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull))
118 #define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8)
119 #define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
120 #define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
121 #define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
122 #define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
123 #define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
124 #define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
125 #define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
126 #define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
127 #define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
128 #define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
129 #define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
130 #define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
131 
135 #ifdef __BIG_ENDIAN_BITFIELD
137  uint64_t len:1;
139  uint64_t bit1:6;
141  uint64_t bit0:6;
143  uint64_t skip3:7;
145  uint64_t skip2:7;
147  uint64_t skip1:7;
148 #else
161 #endif
162  } s;
167 };
168 
172 #ifdef __BIG_ENDIAN_BITFIELD
173  uint64_t bckprs:1;
175  uint64_t hiwater:5;
177  uint64_t lowater:5;
178 #else
184 #endif
185  } s;
199 };
200 
204 #ifdef __BIG_ENDIAN_BITFIELD
206  uint64_t bist:22;
207 #else
210 #endif
211  } s;
213 #ifdef __BIG_ENDIAN_BITFIELD
215  uint64_t bist:18;
216 #else
219 #endif
220  } cn30xx;
225 #ifdef __BIG_ENDIAN_BITFIELD
227  uint64_t bist:17;
228 #else
231 #endif
232  } cn50xx;
240 #ifdef __BIG_ENDIAN_BITFIELD
242  uint64_t bist:20;
243 #else
246 #endif
247  } cn61xx;
254 };
255 
259 #ifdef __BIG_ENDIAN_BITFIELD
261  uint64_t upper_tag:16;
262  uint64_t tag:8;
264  uint64_t offset:9;
266  uint64_t skip:7;
267 #else
275 #endif
276  } s;
280 };
281 
285 #ifdef __BIG_ENDIAN_BITFIELD
286  uint64_t pos7_val:1;
287  uint64_t pos7:7;
288  uint64_t pos6_val:1;
289  uint64_t pos6:7;
290  uint64_t pos5_val:1;
291  uint64_t pos5:7;
292  uint64_t pos4_val:1;
293  uint64_t pos4:7;
294  uint64_t pos3_val:1;
295  uint64_t pos3:7;
296  uint64_t pos2_val:1;
297  uint64_t pos2:7;
298  uint64_t pos1_val:1;
299  uint64_t pos1:7;
300  uint64_t pos0_val:1;
301  uint64_t pos0:7;
302 #else
319 #endif
320  } s;
324 };
325 
329 #ifdef __BIG_ENDIAN_BITFIELD
330  uint64_t tag_en:1;
331  uint64_t grp_en:1;
332  uint64_t tt_en:1;
333  uint64_t qos_en:1;
335  uint64_t tag:8;
337  uint64_t grp:6;
339  uint64_t tt:2;
341  uint64_t qos:3;
342 #else
355 #endif
356  } s;
358 #ifdef __BIG_ENDIAN_BITFIELD
359  uint64_t tag_en:1;
360  uint64_t grp_en:1;
361  uint64_t tt_en:1;
362  uint64_t qos_en:1;
364  uint64_t tag:8;
366  uint64_t grp:4;
368  uint64_t tt:2;
370  uint64_t qos:3;
371 #else
384 #endif
385  } cn61xx;
388 };
389 
393 #ifdef __BIG_ENDIAN_BITFIELD
395  uint64_t clken:1;
396 #else
399 #endif
400  } s;
408 };
409 
413 #ifdef __BIG_ENDIAN_BITFIELD
415  uint64_t invres:1;
416  uint64_t reflect:1;
417 #else
421 #endif
422  } s;
427 };
428 
432 #ifdef __BIG_ENDIAN_BITFIELD
434  uint64_t iv:32;
435 #else
438 #endif
439  } s;
444 };
445 
449 #ifdef __BIG_ENDIAN_BITFIELD
451  uint64_t tcp:1;
452  uint64_t udp:1;
453  uint64_t dprt:16;
454 #else
459 #endif
460  } s;
479 };
480 
484 #ifdef __BIG_ENDIAN_BITFIELD
485  uint64_t map15:4;
486  uint64_t map14:4;
487  uint64_t map13:4;
488  uint64_t map12:4;
489  uint64_t map11:4;
490  uint64_t map10:4;
491  uint64_t map9:4;
492  uint64_t map8:4;
493  uint64_t map7:4;
494  uint64_t map6:4;
495  uint64_t map5:4;
496  uint64_t map4:4;
497  uint64_t map3:4;
498  uint64_t map2:4;
499  uint64_t map1:4;
500  uint64_t map0:4;
501 #else
518 #endif
519  } s;
530 };
531 
535 #ifdef __BIG_ENDIAN_BITFIELD
536  uint64_t map15:4;
537  uint64_t map14:4;
538  uint64_t map13:4;
539  uint64_t map12:4;
540  uint64_t map11:4;
541  uint64_t map10:4;
542  uint64_t map9:4;
543  uint64_t map8:4;
544  uint64_t map7:4;
545  uint64_t map6:4;
546  uint64_t map5:4;
547  uint64_t map4:4;
548  uint64_t map3:4;
549  uint64_t map2:4;
550  uint64_t map1:4;
551  uint64_t map0:4;
552 #else
569 #endif
570  } s;
581 };
582 
586 #ifdef __BIG_ENDIAN_BITFIELD
588  uint64_t maxlen:16;
589  uint64_t minlen:16;
590 #else
594 #endif
595  } s;
608 };
609 
613 #ifdef __BIG_ENDIAN_BITFIELD
615  uint64_t tag_syn:1;
616  uint64_t ip6_udp:1;
617  uint64_t max_l2:1;
619  uint64_t raw_shf:3;
621  uint64_t nip_shf:3;
622 #else
631 #endif
632  } s;
651 };
652 
656 #ifdef __BIG_ENDIAN_BITFIELD
658  uint64_t egrp_dis:1;
664  uint64_t ring_en:1;
666  uint64_t ignrs:1;
667  uint64_t vs_wqe:1;
668  uint64_t vs_qos:1;
669  uint64_t l2_mal:1;
670  uint64_t tcp_flag:1;
671  uint64_t l4_len:1;
672  uint64_t l4_chk:1;
673  uint64_t l4_prt:1;
674  uint64_t l4_mal:1;
676  uint64_t ip6_eext:2;
677  uint64_t ip4_opts:1;
678  uint64_t ip_hop:1;
679  uint64_t ip_mal:1;
680  uint64_t ip_chk:1;
681 #else
706 #endif
707  } s;
709 #ifdef __BIG_ENDIAN_BITFIELD
711  uint64_t ignrs:1;
712  uint64_t vs_wqe:1;
713  uint64_t vs_qos:1;
714  uint64_t l2_mal:1;
715  uint64_t tcp_flag:1;
716  uint64_t l4_len:1;
717  uint64_t l4_chk:1;
718  uint64_t l4_prt:1;
719  uint64_t l4_mal:1;
721  uint64_t ip6_eext:2;
722  uint64_t ip4_opts:1;
723  uint64_t ip_hop:1;
724  uint64_t ip_mal:1;
725  uint64_t ip_chk:1;
726 #else
743 #endif
744  } cn30xx;
750 #ifdef __BIG_ENDIAN_BITFIELD
756  uint64_t ring_en:1;
758  uint64_t ignrs:1;
759  uint64_t vs_wqe:1;
760  uint64_t vs_qos:1;
761  uint64_t l2_mal:1;
762  uint64_t tcp_flag:1;
763  uint64_t l4_len:1;
764  uint64_t l4_chk:1;
765  uint64_t l4_prt:1;
766  uint64_t l4_mal:1;
768  uint64_t ip6_eext:2;
769  uint64_t ip4_opts:1;
770  uint64_t ip_hop:1;
771  uint64_t ip_mal:1;
772  uint64_t ip_chk:1;
773 #else
796 #endif
797  } cn52xx;
801 #ifdef __BIG_ENDIAN_BITFIELD
803  uint64_t ring_en:1;
805  uint64_t ignrs:1;
806  uint64_t vs_wqe:1;
807  uint64_t vs_qos:1;
808  uint64_t l2_mal:1;
809  uint64_t tcp_flag:1;
810  uint64_t l4_len:1;
811  uint64_t l4_chk:1;
812  uint64_t l4_prt:1;
813  uint64_t l4_mal:1;
815  uint64_t ip6_eext:2;
816  uint64_t ip4_opts:1;
817  uint64_t ip_hop:1;
818  uint64_t ip_mal:1;
819  uint64_t ip_chk:1;
820 #else
839 #endif
840  } cn56xxp1;
844 #ifdef __BIG_ENDIAN_BITFIELD
851  uint64_t ring_en:1;
853  uint64_t ignrs:1;
854  uint64_t vs_wqe:1;
855  uint64_t vs_qos:1;
856  uint64_t l2_mal:1;
857  uint64_t tcp_flag:1;
858  uint64_t l4_len:1;
859  uint64_t l4_chk:1;
860  uint64_t l4_prt:1;
861  uint64_t l4_mal:1;
863  uint64_t ip6_eext:2;
864  uint64_t ip4_opts:1;
865  uint64_t ip_hop:1;
866  uint64_t ip_mal:1;
867  uint64_t ip_chk:1;
868 #else
892 #endif
893  } cn61xx;
898 #ifdef __BIG_ENDIAN_BITFIELD
900  uint64_t egrp_dis:1;
906  uint64_t ignrs:1;
907  uint64_t vs_wqe:1;
908  uint64_t vs_qos:1;
909  uint64_t l2_mal:1;
910  uint64_t tcp_flag:1;
911  uint64_t l4_len:1;
912  uint64_t l4_chk:1;
913  uint64_t l4_prt:1;
914  uint64_t l4_mal:1;
916  uint64_t ip6_eext:2;
917  uint64_t ip4_opts:1;
918  uint64_t ip_hop:1;
919  uint64_t ip_mal:1;
920  uint64_t ip_chk:1;
921 #else
944 #endif
945  } cn68xx;
947 #ifdef __BIG_ENDIAN_BITFIELD
954  uint64_t ignrs:1;
955  uint64_t vs_wqe:1;
956  uint64_t vs_qos:1;
957  uint64_t l2_mal:1;
958  uint64_t tcp_flag:1;
959  uint64_t l4_len:1;
960  uint64_t l4_chk:1;
961  uint64_t l4_prt:1;
962  uint64_t l4_mal:1;
964  uint64_t ip6_eext:2;
965  uint64_t ip4_opts:1;
966  uint64_t ip_hop:1;
967  uint64_t ip_mal:1;
968  uint64_t ip_chk:1;
969 #else
991 #endif
992  } cn68xxp1;
994 };
995 
999 #ifdef __BIG_ENDIAN_BITFIELD
1001  uint64_t up_qos:1;
1003  uint64_t qos:3;
1005  uint64_t pri:6;
1006 #else
1013 #endif
1014  } s;
1023 };
1024 
1028 #ifdef __BIG_ENDIAN_BITFIELD
1030  uint64_t punyerr:1;
1031  uint64_t lenerr:1;
1032  uint64_t maxerr:1;
1033  uint64_t minerr:1;
1034  uint64_t beperr:1;
1035  uint64_t feperr:1;
1036  uint64_t todoovr:1;
1037  uint64_t skprunt:1;
1038  uint64_t badtag:1;
1039  uint64_t prtnxa:1;
1040  uint64_t bckprs:1;
1041  uint64_t crcerr:1;
1042  uint64_t pktdrp:1;
1043 #else
1058 #endif
1059  } s;
1061 #ifdef __BIG_ENDIAN_BITFIELD
1063  uint64_t beperr:1;
1064  uint64_t feperr:1;
1065  uint64_t todoovr:1;
1066  uint64_t skprunt:1;
1067  uint64_t badtag:1;
1068  uint64_t prtnxa:1;
1069  uint64_t bckprs:1;
1070  uint64_t crcerr:1;
1071  uint64_t pktdrp:1;
1072 #else
1083 #endif
1084  } cn30xx;
1089 #ifdef __BIG_ENDIAN_BITFIELD
1091  uint64_t lenerr:1;
1092  uint64_t maxerr:1;
1093  uint64_t minerr:1;
1094  uint64_t beperr:1;
1095  uint64_t feperr:1;
1096  uint64_t todoovr:1;
1097  uint64_t skprunt:1;
1098  uint64_t badtag:1;
1099  uint64_t prtnxa:1;
1100  uint64_t bckprs:1;
1102  uint64_t pktdrp:1;
1103 #else
1117 #endif
1118  } cn50xx;
1120 #ifdef __BIG_ENDIAN_BITFIELD
1122  uint64_t punyerr:1;
1123  uint64_t lenerr:1;
1124  uint64_t maxerr:1;
1125  uint64_t minerr:1;
1126  uint64_t beperr:1;
1127  uint64_t feperr:1;
1128  uint64_t todoovr:1;
1129  uint64_t skprunt:1;
1130  uint64_t badtag:1;
1131  uint64_t prtnxa:1;
1132  uint64_t bckprs:1;
1134  uint64_t pktdrp:1;
1135 #else
1150 #endif
1151  } cn52xx;
1155 #ifdef __BIG_ENDIAN_BITFIELD
1157  uint64_t lenerr:1;
1158  uint64_t maxerr:1;
1159  uint64_t minerr:1;
1160  uint64_t beperr:1;
1161  uint64_t feperr:1;
1162  uint64_t todoovr:1;
1163  uint64_t skprunt:1;
1164  uint64_t badtag:1;
1165  uint64_t prtnxa:1;
1166  uint64_t bckprs:1;
1167  uint64_t crcerr:1;
1168  uint64_t pktdrp:1;
1169 #else
1183 #endif
1184  } cn56xxp1;
1186 #ifdef __BIG_ENDIAN_BITFIELD
1188  uint64_t punyerr:1;
1190  uint64_t beperr:1;
1191  uint64_t feperr:1;
1192  uint64_t todoovr:1;
1193  uint64_t skprunt:1;
1194  uint64_t badtag:1;
1195  uint64_t prtnxa:1;
1196  uint64_t bckprs:1;
1197  uint64_t crcerr:1;
1198  uint64_t pktdrp:1;
1199 #else
1212 #endif
1213  } cn58xx;
1222 };
1223 
1227 #ifdef __BIG_ENDIAN_BITFIELD
1229  uint64_t punyerr:1;
1230  uint64_t lenerr:1;
1231  uint64_t maxerr:1;
1232  uint64_t minerr:1;
1233  uint64_t beperr:1;
1234  uint64_t feperr:1;
1235  uint64_t todoovr:1;
1236  uint64_t skprunt:1;
1237  uint64_t badtag:1;
1238  uint64_t prtnxa:1;
1239  uint64_t bckprs:1;
1240  uint64_t crcerr:1;
1241  uint64_t pktdrp:1;
1242 #else
1257 #endif
1258  } s;
1260 #ifdef __BIG_ENDIAN_BITFIELD
1262  uint64_t beperr:1;
1263  uint64_t feperr:1;
1264  uint64_t todoovr:1;
1265  uint64_t skprunt:1;
1266  uint64_t badtag:1;
1267  uint64_t prtnxa:1;
1268  uint64_t bckprs:1;
1269  uint64_t crcerr:1;
1270  uint64_t pktdrp:1;
1271 #else
1282 #endif
1283  } cn30xx;
1288 #ifdef __BIG_ENDIAN_BITFIELD
1290  uint64_t lenerr:1;
1291  uint64_t maxerr:1;
1292  uint64_t minerr:1;
1293  uint64_t beperr:1;
1294  uint64_t feperr:1;
1295  uint64_t todoovr:1;
1296  uint64_t skprunt:1;
1297  uint64_t badtag:1;
1298  uint64_t prtnxa:1;
1299  uint64_t bckprs:1;
1301  uint64_t pktdrp:1;
1302 #else
1316 #endif
1317  } cn50xx;
1319 #ifdef __BIG_ENDIAN_BITFIELD
1321  uint64_t punyerr:1;
1322  uint64_t lenerr:1;
1323  uint64_t maxerr:1;
1324  uint64_t minerr:1;
1325  uint64_t beperr:1;
1326  uint64_t feperr:1;
1327  uint64_t todoovr:1;
1328  uint64_t skprunt:1;
1329  uint64_t badtag:1;
1330  uint64_t prtnxa:1;
1331  uint64_t bckprs:1;
1333  uint64_t pktdrp:1;
1334 #else
1349 #endif
1350  } cn52xx;
1354 #ifdef __BIG_ENDIAN_BITFIELD
1356  uint64_t lenerr:1;
1357  uint64_t maxerr:1;
1358  uint64_t minerr:1;
1359  uint64_t beperr:1;
1360  uint64_t feperr:1;
1361  uint64_t todoovr:1;
1362  uint64_t skprunt:1;
1363  uint64_t badtag:1;
1364  uint64_t prtnxa:1;
1365  uint64_t bckprs:1;
1366  uint64_t crcerr:1;
1367  uint64_t pktdrp:1;
1368 #else
1382 #endif
1383  } cn56xxp1;
1385 #ifdef __BIG_ENDIAN_BITFIELD
1387  uint64_t punyerr:1;
1389  uint64_t beperr:1;
1390  uint64_t feperr:1;
1391  uint64_t todoovr:1;
1392  uint64_t skprunt:1;
1393  uint64_t badtag:1;
1394  uint64_t prtnxa:1;
1395  uint64_t bckprs:1;
1396  uint64_t crcerr:1;
1397  uint64_t pktdrp:1;
1398 #else
1411 #endif
1412  } cn58xx;
1421 };
1422 
1426 #ifdef __BIG_ENDIAN_BITFIELD
1428  uint64_t offset:3;
1429 #else
1432 #endif
1433  } s;
1452 };
1453 
1457 #ifdef __BIG_ENDIAN_BITFIELD
1458  uint64_t diff2_padd:8;
1459  uint64_t hg2_padd:8;
1460  uint64_t vlan2_padd:8;
1462  uint64_t diff2_bpid:6;
1464  uint64_t hg2_bpid:6;
1466  uint64_t vlan2_bpid:6;
1468  uint64_t diff2_qos:3;
1470  uint64_t hg2_qos:3;
1472  uint64_t vlan2_qos:3;
1473 #else
1489 #endif
1490  } s;
1493 };
1494 
1498 #ifdef __BIG_ENDIAN_BITFIELD
1500  uint64_t ih_pri:1;
1502  uint64_t pad_len:1;
1503  uint64_t vlan_len:1;
1504  uint64_t lenerr_en:1;
1505  uint64_t maxerr_en:1;
1506  uint64_t minerr_en:1;
1507  uint64_t grp_wat_47:4;
1508  uint64_t qos_wat_47:4;
1510  uint64_t rawdrp:1;
1511  uint64_t tag_inc:2;
1512  uint64_t dyn_rs:1;
1513  uint64_t inst_hdr:1;
1514  uint64_t grp_wat:4;
1515  uint64_t hg_qos:1;
1516  uint64_t qos:3;
1517  uint64_t qos_wat:4;
1518  uint64_t qos_vsel:1;
1519  uint64_t qos_vod:1;
1520  uint64_t qos_diff:1;
1521  uint64_t qos_vlan:1;
1523  uint64_t crc_en:1;
1524  uint64_t higig_en:1;
1525  uint64_t dsa_en:1;
1526  uint64_t mode:2;
1528  uint64_t skip:7;
1529 #else
1560 #endif
1561  } s;
1563 #ifdef __BIG_ENDIAN_BITFIELD
1565  uint64_t rawdrp:1;
1566  uint64_t tag_inc:2;
1567  uint64_t dyn_rs:1;
1568  uint64_t inst_hdr:1;
1569  uint64_t grp_wat:4;
1571  uint64_t qos:3;
1572  uint64_t qos_wat:4;
1574  uint64_t qos_diff:1;
1575  uint64_t qos_vlan:1;
1577  uint64_t mode:2;
1579  uint64_t skip:7;
1580 #else
1597 #endif
1598  } cn30xx;
1601 #ifdef __BIG_ENDIAN_BITFIELD
1603  uint64_t rawdrp:1;
1604  uint64_t tag_inc:2;
1605  uint64_t dyn_rs:1;
1606  uint64_t inst_hdr:1;
1607  uint64_t grp_wat:4;
1609  uint64_t qos:3;
1610  uint64_t qos_wat:4;
1612  uint64_t qos_diff:1;
1613  uint64_t qos_vlan:1;
1615  uint64_t crc_en:1;
1617  uint64_t mode:2;
1619  uint64_t skip:7;
1620 #else
1639 #endif
1640  } cn38xx;
1643 #ifdef __BIG_ENDIAN_BITFIELD
1645  uint64_t pad_len:1;
1646  uint64_t vlan_len:1;
1647  uint64_t lenerr_en:1;
1648  uint64_t maxerr_en:1;
1649  uint64_t minerr_en:1;
1650  uint64_t grp_wat_47:4;
1651  uint64_t qos_wat_47:4;
1653  uint64_t rawdrp:1;
1654  uint64_t tag_inc:2;
1655  uint64_t dyn_rs:1;
1656  uint64_t inst_hdr:1;
1657  uint64_t grp_wat:4;
1659  uint64_t qos:3;
1660  uint64_t qos_wat:4;
1662  uint64_t qos_vod:1;
1663  uint64_t qos_diff:1;
1664  uint64_t qos_vlan:1;
1666  uint64_t crc_en:1;
1668  uint64_t mode:2;
1670  uint64_t skip:7;
1671 #else
1699 #endif
1700  } cn50xx;
1702 #ifdef __BIG_ENDIAN_BITFIELD
1704  uint64_t pad_len:1;
1705  uint64_t vlan_len:1;
1706  uint64_t lenerr_en:1;
1707  uint64_t maxerr_en:1;
1708  uint64_t minerr_en:1;
1709  uint64_t grp_wat_47:4;
1710  uint64_t qos_wat_47:4;
1712  uint64_t rawdrp:1;
1713  uint64_t tag_inc:2;
1714  uint64_t dyn_rs:1;
1715  uint64_t inst_hdr:1;
1716  uint64_t grp_wat:4;
1717  uint64_t hg_qos:1;
1718  uint64_t qos:3;
1719  uint64_t qos_wat:4;
1720  uint64_t qos_vsel:1;
1721  uint64_t qos_vod:1;
1722  uint64_t qos_diff:1;
1723  uint64_t qos_vlan:1;
1725  uint64_t crc_en:1;
1726  uint64_t higig_en:1;
1727  uint64_t dsa_en:1;
1728  uint64_t mode:2;
1730  uint64_t skip:7;
1731 #else
1760 #endif
1761  } cn52xx;
1766 #ifdef __BIG_ENDIAN_BITFIELD
1768  uint64_t rawdrp:1;
1769  uint64_t tag_inc:2;
1770  uint64_t dyn_rs:1;
1771  uint64_t inst_hdr:1;
1772  uint64_t grp_wat:4;
1774  uint64_t qos:3;
1775  uint64_t qos_wat:4;
1777  uint64_t qos_vod:1;
1778  uint64_t qos_diff:1;
1779  uint64_t qos_vlan:1;
1781  uint64_t crc_en:1;
1783  uint64_t mode:2;
1785  uint64_t skip:7;
1786 #else
1806 #endif
1807  } cn58xx;
1814 #ifdef __BIG_ENDIAN_BITFIELD
1816  uint64_t ih_pri:1;
1818  uint64_t pad_len:1;
1819  uint64_t vlan_len:1;
1820  uint64_t lenerr_en:1;
1821  uint64_t maxerr_en:1;
1822  uint64_t minerr_en:1;
1823  uint64_t grp_wat_47:4;
1824  uint64_t qos_wat_47:4;
1826  uint64_t rawdrp:1;
1827  uint64_t tag_inc:2;
1828  uint64_t dyn_rs:1;
1829  uint64_t inst_hdr:1;
1830  uint64_t grp_wat:4;
1831  uint64_t hg_qos:1;
1832  uint64_t qos:3;
1833  uint64_t qos_wat:4;
1835  uint64_t qos_vod:1;
1836  uint64_t qos_diff:1;
1837  uint64_t qos_vlan:1;
1839  uint64_t crc_en:1;
1840  uint64_t higig_en:1;
1841  uint64_t dsa_en:1;
1842  uint64_t mode:2;
1844  uint64_t skip:7;
1845 #else
1876 #endif
1877  } cn68xx;
1880 };
1881 
1885 #ifdef __BIG_ENDIAN_BITFIELD
1888  uint64_t alt_skp_en:1;
1890  uint64_t bsel_num:2;
1891  uint64_t bsel_en:1;
1893  uint64_t base:8;
1895  uint64_t bpid:6;
1896 #else
1907 #endif
1908  } s;
1910 #ifdef __BIG_ENDIAN_BITFIELD
1913  uint64_t alt_skp_en:1;
1915  uint64_t bsel_num:2;
1916  uint64_t bsel_en:1;
1918 #else
1926 #endif
1927  } cn61xx;
1929 #ifdef __BIG_ENDIAN_BITFIELD
1932  uint64_t alt_skp_en:1;
1934 #else
1939 #endif
1940  } cn66xx;
1943 #ifdef __BIG_ENDIAN_BITFIELD
1945  uint64_t base:8;
1947  uint64_t bpid:6;
1948 #else
1953 #endif
1954  } cn68xxp1;
1956 };
1957 
1961 #ifdef __BIG_ENDIAN_BITFIELD
1963  uint64_t portadd_en:1;
1964  uint64_t inc_hwchk:1;
1970  uint64_t grp_msb:2;
1971  uint64_t grptagbase:4;
1972  uint64_t grptagmask:4;
1973  uint64_t grptag:1;
1975  uint64_t tag_mode:2;
1976  uint64_t inc_vs:2;
1977  uint64_t inc_vlan:1;
1994  uint64_t grp:4;
1995 #else
2029 #endif
2030  } s;
2032 #ifdef __BIG_ENDIAN_BITFIELD
2034  uint64_t grptagbase:4;
2035  uint64_t grptagmask:4;
2036  uint64_t grptag:1;
2038  uint64_t tag_mode:2;
2039  uint64_t inc_vs:2;
2040  uint64_t inc_vlan:1;
2057  uint64_t grp:4;
2058 #else
2084 #endif
2085  } cn30xx;
2090 #ifdef __BIG_ENDIAN_BITFIELD
2092  uint64_t grptagbase:4;
2093  uint64_t grptagmask:4;
2094  uint64_t grptag:1;
2096  uint64_t tag_mode:2;
2097  uint64_t inc_vs:2;
2098  uint64_t inc_vlan:1;
2115  uint64_t grp:4;
2116 #else
2142 #endif
2143  } cn50xx;
2157 };
2158 
2162 #ifdef __BIG_ENDIAN_BITFIELD
2164  uint64_t qos:3;
2165 #else
2168 #endif
2169  } s;
2186 };
2187 
2191 #ifdef __BIG_ENDIAN_BITFIELD
2193  uint64_t qos1:3;
2195  uint64_t qos:3;
2196 #else
2201 #endif
2202  } s;
2204 #ifdef __BIG_ENDIAN_BITFIELD
2206  uint64_t qos:3;
2207 #else
2210 #endif
2211  } cn30xx;
2227 };
2228 
2232 #ifdef __BIG_ENDIAN_BITFIELD
2234  uint64_t mask:16;
2236  uint64_t grp:6;
2238  uint64_t qos:3;
2240  uint64_t match_type:3;
2241  uint64_t match_value:16;
2242 #else
2252 #endif
2253  } s;
2255 #ifdef __BIG_ENDIAN_BITFIELD
2257  uint64_t mask:16;
2259  uint64_t grp:4;
2261  uint64_t qos:3;
2263  uint64_t match_type:2;
2264  uint64_t match_value:16;
2265 #else
2275 #endif
2276  } cn30xx;
2281 #ifdef __BIG_ENDIAN_BITFIELD
2283  uint64_t mask:16;
2285  uint64_t grp:4;
2287  uint64_t qos:3;
2289  uint64_t match_type:3;
2290  uint64_t match_value:16;
2291 #else
2301 #endif
2302  } cn50xx;
2316 };
2317 
2321 #ifdef __BIG_ENDIAN_BITFIELD
2323  uint64_t word:56;
2324 #else
2327 #endif
2328  } s;
2347 };
2348 
2352 #ifdef __BIG_ENDIAN_BITFIELD
2354  uint64_t rst:1;
2355 #else
2358 #endif
2359  } s;
2377 };
2378 
2382 #ifdef __BIG_ENDIAN_BITFIELD
2383  uint64_t drp_pkts:32;
2384  uint64_t drp_octs:32;
2385 #else
2388 #endif
2389  } s;
2392 };
2393 
2397 #ifdef __BIG_ENDIAN_BITFIELD
2398  uint64_t drp_pkts:32;
2399  uint64_t drp_octs:32;
2400 #else
2403 #endif
2404  } s;
2421 };
2422 
2426 #ifdef __BIG_ENDIAN_BITFIELD
2427  uint64_t bcast:32;
2428  uint64_t mcast:32;
2429 #else
2432 #endif
2433  } s;
2436 };
2437 
2441 #ifdef __BIG_ENDIAN_BITFIELD
2442  uint64_t bcast:32;
2443  uint64_t mcast:32;
2444 #else
2447 #endif
2448  } s;
2458 };
2459 
2463 #ifdef __BIG_ENDIAN_BITFIELD
2464  uint64_t bcast:32;
2465  uint64_t mcast:32;
2466 #else
2469 #endif
2470  } s;
2473 };
2474 
2478 #ifdef __BIG_ENDIAN_BITFIELD
2479  uint64_t bcast:32;
2480  uint64_t mcast:32;
2481 #else
2484 #endif
2485  } s;
2495 };
2496 
2500 #ifdef __BIG_ENDIAN_BITFIELD
2502  uint64_t octs:48;
2503 #else
2506 #endif
2507  } s;
2510 };
2511 
2515 #ifdef __BIG_ENDIAN_BITFIELD
2517  uint64_t octs:48;
2518 #else
2521 #endif
2522  } s;
2539 };
2540 
2544 #ifdef __BIG_ENDIAN_BITFIELD
2545  uint64_t pkts:32;
2546  uint64_t raw:32;
2547 #else
2550 #endif
2551  } s;
2554 };
2555 
2559 #ifdef __BIG_ENDIAN_BITFIELD
2560  uint64_t pkts:32;
2561  uint64_t raw:32;
2562 #else
2565 #endif
2566  } s;
2583 };
2584 
2588 #ifdef __BIG_ENDIAN_BITFIELD
2589  uint64_t bcst:32;
2590  uint64_t mcst:32;
2591 #else
2594 #endif
2595  } s;
2598 };
2599 
2603 #ifdef __BIG_ENDIAN_BITFIELD
2604  uint64_t bcst:32;
2605  uint64_t mcst:32;
2606 #else
2609 #endif
2610  } s;
2627 };
2628 
2632 #ifdef __BIG_ENDIAN_BITFIELD
2633  uint64_t h65to127:32;
2634  uint64_t h64:32;
2635 #else
2638 #endif
2639  } s;
2642 };
2643 
2647 #ifdef __BIG_ENDIAN_BITFIELD
2648  uint64_t h65to127:32;
2649  uint64_t h64:32;
2650 #else
2653 #endif
2654  } s;
2671 };
2672 
2676 #ifdef __BIG_ENDIAN_BITFIELD
2677  uint64_t h256to511:32;
2678  uint64_t h128to255:32;
2679 #else
2682 #endif
2683  } s;
2686 };
2687 
2691 #ifdef __BIG_ENDIAN_BITFIELD
2692  uint64_t h256to511:32;
2693  uint64_t h128to255:32;
2694 #else
2697 #endif
2698  } s;
2715 };
2716 
2720 #ifdef __BIG_ENDIAN_BITFIELD
2721  uint64_t h1024to1518:32;
2722  uint64_t h512to1023:32;
2723 #else
2726 #endif
2727  } s;
2730 };
2731 
2735 #ifdef __BIG_ENDIAN_BITFIELD
2736  uint64_t h1024to1518:32;
2737  uint64_t h512to1023:32;
2738 #else
2741 #endif
2742  } s;
2759 };
2760 
2764 #ifdef __BIG_ENDIAN_BITFIELD
2765  uint64_t fcs:32;
2766  uint64_t h1519:32;
2767 #else
2770 #endif
2771  } s;
2774 };
2775 
2779 #ifdef __BIG_ENDIAN_BITFIELD
2780  uint64_t fcs:32;
2781  uint64_t h1519:32;
2782 #else
2785 #endif
2786  } s;
2803 };
2804 
2808 #ifdef __BIG_ENDIAN_BITFIELD
2809  uint64_t frag:32;
2810  uint64_t undersz:32;
2811 #else
2814 #endif
2815  } s;
2818 };
2819 
2823 #ifdef __BIG_ENDIAN_BITFIELD
2824  uint64_t frag:32;
2825  uint64_t undersz:32;
2826 #else
2829 #endif
2830  } s;
2847 };
2848 
2852 #ifdef __BIG_ENDIAN_BITFIELD
2853  uint64_t jabber:32;
2854  uint64_t oversz:32;
2855 #else
2858 #endif
2859  } s;
2862 };
2863 
2867 #ifdef __BIG_ENDIAN_BITFIELD
2868  uint64_t jabber:32;
2869  uint64_t oversz:32;
2870 #else
2873 #endif
2874  } s;
2891 };
2892 
2896 #ifdef __BIG_ENDIAN_BITFIELD
2898  uint64_t mode:1;
2900  uint64_t rdclr:1;
2901 #else
2906 #endif
2907  } s;
2909 #ifdef __BIG_ENDIAN_BITFIELD
2911  uint64_t rdclr:1;
2912 #else
2915 #endif
2916  } cn30xx;
2934 };
2935 
2939 #ifdef __BIG_ENDIAN_BITFIELD
2941  uint64_t errs:16;
2942 #else
2945 #endif
2946  } s;
2963 };
2964 
2968 #ifdef __BIG_ENDIAN_BITFIELD
2970  uint64_t errs:16;
2971 #else
2974 #endif
2975  } s;
2978 };
2979 
2983 #ifdef __BIG_ENDIAN_BITFIELD
2985  uint64_t octs:48;
2986 #else
2989 #endif
2990  } s;
3007 };
3008 
3012 #ifdef __BIG_ENDIAN_BITFIELD
3014  uint64_t octs:48;
3015 #else
3018 #endif
3019  } s;
3022 };
3023 
3027 #ifdef __BIG_ENDIAN_BITFIELD
3029  uint64_t pkts:32;
3030 #else
3033 #endif
3034  } s;
3051 };
3052 
3056 #ifdef __BIG_ENDIAN_BITFIELD
3058  uint64_t pkts:32;
3059 #else
3062 #endif
3063  } s;
3066 };
3067 
3071 #ifdef __BIG_ENDIAN_BITFIELD
3072  uint64_t port_bit:64;
3073 #else
3075 #endif
3076  } s;
3079 };
3080 
3084 #ifdef __BIG_ENDIAN_BITFIELD
3086  uint64_t en:8;
3087 #else
3090 #endif
3091  } s;
3110 };
3111 
3115 #ifdef __BIG_ENDIAN_BITFIELD
3117  uint64_t mask:16;
3118 #else
3121 #endif
3122  } s;
3141 };
3142 
3146 #ifdef __BIG_ENDIAN_BITFIELD
3148  uint64_t dst:16;
3149  uint64_t src:16;
3150 #else
3154 #endif
3155  } s;
3174 };
3175 
3179 #ifdef __BIG_ENDIAN_BITFIELD
3180  uint64_t val:1;
3182  uint64_t entry:62;
3183 #else
3187 #endif
3188  } s;
3207 };
3208 
3212 #ifdef __BIG_ENDIAN_BITFIELD
3213  uint64_t type3:16;
3214  uint64_t type2:16;
3215  uint64_t type1:16;
3216  uint64_t type0:16;
3217 #else
3222 #endif
3223  } s;
3228 };
3229 
3233 #ifdef __BIG_ENDIAN_BITFIELD
3234  uint64_t drp_pkts:32;
3235  uint64_t drp_octs:32;
3236 #else
3239 #endif
3240  } s;
3244 };
3245 
3249 #ifdef __BIG_ENDIAN_BITFIELD
3250  uint64_t bcast:32;
3251  uint64_t mcast:32;
3252 #else
3255 #endif
3256  } s;
3260 };
3261 
3265 #ifdef __BIG_ENDIAN_BITFIELD
3266  uint64_t bcast:32;
3267  uint64_t mcast:32;
3268 #else
3271 #endif
3272  } s;
3276 };
3277 
3281 #ifdef __BIG_ENDIAN_BITFIELD
3283  uint64_t octs:48;
3284 #else
3287 #endif
3288  } s;
3292 };
3293 
3297 #ifdef __BIG_ENDIAN_BITFIELD
3298  uint64_t pkts:32;
3299  uint64_t raw:32;
3300 #else
3303 #endif
3304  } s;
3308 };
3309 
3313 #ifdef __BIG_ENDIAN_BITFIELD
3314  uint64_t bcst:32;
3315  uint64_t mcst:32;
3316 #else
3319 #endif
3320  } s;
3324 };
3325 
3329 #ifdef __BIG_ENDIAN_BITFIELD
3330  uint64_t h65to127:32;
3331  uint64_t h64:32;
3332 #else
3335 #endif
3336  } s;
3340 };
3341 
3345 #ifdef __BIG_ENDIAN_BITFIELD
3346  uint64_t h256to511:32;
3347  uint64_t h128to255:32;
3348 #else
3351 #endif
3352  } s;
3356 };
3357 
3361 #ifdef __BIG_ENDIAN_BITFIELD
3362  uint64_t h1024to1518:32;
3363  uint64_t h512to1023:32;
3364 #else
3367 #endif
3368  } s;
3372 };
3373 
3377 #ifdef __BIG_ENDIAN_BITFIELD
3378  uint64_t fcs:32;
3379  uint64_t h1519:32;
3380 #else
3383 #endif
3384  } s;
3388 };
3389 
3393 #ifdef __BIG_ENDIAN_BITFIELD
3394  uint64_t frag:32;
3395  uint64_t undersz:32;
3396 #else
3399 #endif
3400  } s;
3404 };
3405 
3409 #ifdef __BIG_ENDIAN_BITFIELD
3410  uint64_t jabber:32;
3411  uint64_t oversz:32;
3412 #else
3415 #endif
3416  } s;
3420 };
3421 
3422 #endif