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cvmx-srxx-defs.h
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1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: [email protected]
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
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15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT. See the GNU General Public License for more
17  * details.
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21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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23  *
24  * This file may also be available under a different license from Cavium.
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26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_SRXX_DEFS_H__
29 #define __CVMX_SRXX_DEFS_H__
30 
31 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
32 #define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
33 #define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
34 #define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
36 #define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
37 
41 #ifdef __BIG_ENDIAN_BITFIELD
43  uint64_t prts:4;
44  uint64_t st_en:1;
46  uint64_t inf_en:1;
47 #else
53 #endif
54  } s;
59 };
60 
64 #ifdef __BIG_ENDIAN_BITFIELD
66  uint64_t ignore:16;
67 #else
70 #endif
71  } s;
76 };
77 
81 #ifdef __BIG_ENDIAN_BITFIELD
83  uint64_t oddpar:1;
84  uint64_t prt3:4;
85  uint64_t prt2:4;
86  uint64_t prt1:4;
87  uint64_t prt0:4;
88 #else
95 #endif
96  } s;
101 };
102 
106 #ifdef __BIG_ENDIAN_BITFIELD
108  uint64_t m:8;
110  uint64_t len:7;
111 #else
116 #endif
117  } s;
122 };
123 
127 #ifdef __BIG_ENDIAN_BITFIELD
129  uint64_t eop:1;
130  uint64_t sop:1;
131  uint64_t mod:4;
132  uint64_t opc:4;
133  uint64_t adr:4;
134 #else
141 #endif
142  } s;
146 };
147 
151 #ifdef __BIG_ENDIAN_BITFIELD
152  uint64_t dat:64;
153 #else
155 #endif
156  } s;
160 };
161 
162 #endif