31 #define CX18_PROC_SOFT_RESET 0xc70010
32 #define CX18_DDR_SOFT_RESET 0xc70014
33 #define CX18_CLOCK_SELECT1 0xc71000
34 #define CX18_CLOCK_SELECT2 0xc71004
35 #define CX18_HALF_CLOCK_SELECT1 0xc71008
36 #define CX18_HALF_CLOCK_SELECT2 0xc7100C
37 #define CX18_CLOCK_POLARITY1 0xc71010
38 #define CX18_CLOCK_POLARITY2 0xc71014
39 #define CX18_ADD_DELAY_ENABLE1 0xc71018
40 #define CX18_ADD_DELAY_ENABLE2 0xc7101C
41 #define CX18_CLOCK_ENABLE1 0xc71020
42 #define CX18_CLOCK_ENABLE2 0xc71024
44 #define CX18_REG_BUS_TIMEOUT_EN 0xc72024
46 #define CX18_FAST_CLOCK_PLL_INT 0xc78000
47 #define CX18_FAST_CLOCK_PLL_FRAC 0xc78004
48 #define CX18_FAST_CLOCK_PLL_POST 0xc78008
49 #define CX18_FAST_CLOCK_PLL_PRESCALE 0xc7800C
50 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
52 #define CX18_SLOW_CLOCK_PLL_INT 0xc78014
53 #define CX18_SLOW_CLOCK_PLL_FRAC 0xc78018
54 #define CX18_SLOW_CLOCK_PLL_POST 0xc7801C
55 #define CX18_MPEG_CLOCK_PLL_INT 0xc78040
56 #define CX18_MPEG_CLOCK_PLL_FRAC 0xc78044
57 #define CX18_MPEG_CLOCK_PLL_POST 0xc78048
58 #define CX18_PLL_POWER_DOWN 0xc78088
59 #define CX18_SW1_INT_STATUS 0xc73104
60 #define CX18_SW1_INT_ENABLE_PCI 0xc7311C
61 #define CX18_SW2_INT_SET 0xc73140
62 #define CX18_SW2_INT_STATUS 0xc73144
63 #define CX18_ADEC_CONTROL 0xc78120
65 #define CX18_DDR_REQUEST_ENABLE 0xc80000
66 #define CX18_DDR_CHIP_CONFIG 0xc80004
67 #define CX18_DDR_REFRESH 0xc80008
68 #define CX18_DDR_TIMING1 0xc8000C
69 #define CX18_DDR_TIMING2 0xc80010
70 #define CX18_DDR_POWER_REG 0xc8001C
72 #define CX18_DDR_TUNE_LANE 0xc80048
73 #define CX18_DDR_INITIAL_EMRS 0xc80054
74 #define CX18_DDR_MB_PER_ROW_7 0xc8009C
75 #define CX18_DDR_BASE_63_ADDR 0xc804FC
77 #define CX18_WMB_CLIENT02 0xc90108
78 #define CX18_WMB_CLIENT05 0xc90114
79 #define CX18_WMB_CLIENT06 0xc90118
80 #define CX18_WMB_CLIENT07 0xc9011C
81 #define CX18_WMB_CLIENT08 0xc90120
82 #define CX18_WMB_CLIENT09 0xc90124
83 #define CX18_WMB_CLIENT10 0xc90128
84 #define CX18_WMB_CLIENT11 0xc9012C
85 #define CX18_WMB_CLIENT12 0xc90130
86 #define CX18_WMB_CLIENT13 0xc90134
87 #define CX18_WMB_CLIENT14 0xc90138
89 #define CX18_DSP0_INTERRUPT_MASK 0xd0004C
91 #define APU_ROM_SYNC1 0x6D676553
92 #define APU_ROM_SYNC2 0x72646548
110 CX18_ERR(
"Unable to open firmware %s\n", fn);
111 CX18_ERR(
"Did you put the firmware in the hotplug firmware directory?\n");
117 for (i = 0; i < fw->
size; i += 4096) {
119 for (j = i; j < fw->
size && j < i + 4096; j += 4) {
121 cx18_raw_writel(cx, *src, dst);
122 if (cx18_raw_readl(cx, dst) != *src) {
123 CX18_ERR(
"Mismatch at offset %x\n", i);
140 static int load_apu_fw_direct(
const char *fn,
u8 __iomem *dst,
struct cx18 *cx,
154 CX18_ERR(
"unable to open firmware %s\n", fn);
155 CX18_ERR(
"did you put the firmware in the hotplug firmware directory?\n");
162 vers = fw->
data +
sizeof(seghdr);
165 apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
166 while (offset +
sizeof(seghdr) < fw->
size) {
167 const u32 *shptr = src + offset / 4;
174 offset +=
sizeof(seghdr);
177 offset += seghdr.size;
181 seghdr.addr + seghdr.size - 1);
182 if (*entry_addr == 0)
183 *entry_addr = seghdr.addr;
184 if (offset + seghdr.size > sz)
186 for (i = 0; i < seghdr.size; i += 4096) {
188 for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
190 cx18_raw_writel(cx, src[(offset + j) / 4],
191 dst + seghdr.addr + j);
192 if (cx18_raw_readl(cx, dst + seghdr.addr + j)
193 != src[(offset + j) / 4]) {
202 offset += seghdr.size;
205 CX18_INFO(
"loaded %s firmware V%08x (%zd bytes)\n",
206 fn, apu_version, fw->
size);
217 0x0000000F, 0x000F000F);
219 0x00000002, 0x00020002);
230 0x00000000, 0x00020002);
272 cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
283 cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
310 0x00000020, 0xFFFFFFFF);
312 0x00000004, 0xFFFFFFFF);
316 0x00000004, 0x00060006);
318 0x00000006, 0x00060006);
322 0x00000002, 0xFFFFFFFF);
324 0x00000104, 0xFFFFFFFF);
326 0x00009026, 0xFFFFFFFF);
328 0x00003105, 0xFFFFFFFF);
335 0x00000000, 0x00010001);
355 0x00000000, 0x00020002);
362 0x00000001, 0x00010001);
379 #define CX18_CPU_FIRMWARE "v4l-cx23418-cpu.fw"
380 #define CX18_APU_FIRMWARE "v4l-cx23418-apu.fw"
393 0x0000000F, 0x000F000F);
399 CX18_ERR(
"%s: couldn't stop CPU to load firmware\n", __func__);
421 0x00000000, 0x00080008);
433 CX18_ERR(
"Could not start the CPU\n");
454 cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);