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23 #define HW2_I2C1_INT (1 << 22)
24 #define HW2_I2C2_INT (1 << 23)
25 #define HW2_INT_CLR_STATUS 0xc730c4
26 #define HW2_INT_MASK5_PCI 0xc730e4
27 #define SW1_INT_SET 0xc73100
28 #define SW1_INT_STATUS 0xc73104
29 #define SW1_INT_ENABLE_PCI 0xc7311c
30 #define SW2_INT_SET 0xc73140
31 #define SW2_INT_STATUS 0xc73144
32 #define SW2_INT_ENABLE_CPU 0xc73158
33 #define SW2_INT_ENABLE_PCI 0xc7315c