Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
cx18-scb.h
Go to the documentation of this file.
1 /*
2  * cx18 System Control Block initialization
3  *
4  * Copyright (C) 2007 Hans Verkuil <[email protected]>
5  * Copyright (C) 2008 Andy Walls <[email protected]>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20  * 02111-1307 USA
21  */
22 
23 #ifndef CX18_SCB_H
24 #define CX18_SCB_H
25 
26 #include "cx18-mailbox.h"
27 
28 /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
29  are in the SW1 register. */
30 
31 #define IRQ_APU_TO_CPU 0x00000001
32 #define IRQ_CPU_TO_APU_ACK 0x00000001
33 #define IRQ_HPU_TO_CPU 0x00000002
34 #define IRQ_CPU_TO_HPU_ACK 0x00000002
35 #define IRQ_PPU_TO_CPU 0x00000004
36 #define IRQ_CPU_TO_PPU_ACK 0x00000004
37 #define IRQ_EPU_TO_CPU 0x00000008
38 #define IRQ_CPU_TO_EPU_ACK 0x00000008
39 
40 #define IRQ_CPU_TO_APU 0x00000010
41 #define IRQ_APU_TO_CPU_ACK 0x00000010
42 #define IRQ_HPU_TO_APU 0x00000020
43 #define IRQ_APU_TO_HPU_ACK 0x00000020
44 #define IRQ_PPU_TO_APU 0x00000040
45 #define IRQ_APU_TO_PPU_ACK 0x00000040
46 #define IRQ_EPU_TO_APU 0x00000080
47 #define IRQ_APU_TO_EPU_ACK 0x00000080
48 
49 #define IRQ_CPU_TO_HPU 0x00000100
50 #define IRQ_HPU_TO_CPU_ACK 0x00000100
51 #define IRQ_APU_TO_HPU 0x00000200
52 #define IRQ_HPU_TO_APU_ACK 0x00000200
53 #define IRQ_PPU_TO_HPU 0x00000400
54 #define IRQ_HPU_TO_PPU_ACK 0x00000400
55 #define IRQ_EPU_TO_HPU 0x00000800
56 #define IRQ_HPU_TO_EPU_ACK 0x00000800
57 
58 #define IRQ_CPU_TO_PPU 0x00001000
59 #define IRQ_PPU_TO_CPU_ACK 0x00001000
60 #define IRQ_APU_TO_PPU 0x00002000
61 #define IRQ_PPU_TO_APU_ACK 0x00002000
62 #define IRQ_HPU_TO_PPU 0x00004000
63 #define IRQ_PPU_TO_HPU_ACK 0x00004000
64 #define IRQ_EPU_TO_PPU 0x00008000
65 #define IRQ_PPU_TO_EPU_ACK 0x00008000
66 
67 #define IRQ_CPU_TO_EPU 0x00010000
68 #define IRQ_EPU_TO_CPU_ACK 0x00010000
69 #define IRQ_APU_TO_EPU 0x00020000
70 #define IRQ_EPU_TO_APU_ACK 0x00020000
71 #define IRQ_HPU_TO_EPU 0x00040000
72 #define IRQ_EPU_TO_HPU_ACK 0x00040000
73 #define IRQ_PPU_TO_EPU 0x00080000
74 #define IRQ_EPU_TO_PPU_ACK 0x00080000
75 
76 #define SCB_OFFSET 0xDC0000
77 
78 /* If Firmware uses fixed memory map, it shall not allocate the area
79  between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
80 #define SCB_RESERVED_SIZE 0x10000
81 
82 
83 /* This structure is used by EPU to provide memory descriptors in its memory */
84 struct cx18_mdl_ent {
85  u32 paddr; /* Physical address of a buffer segment */
86  u32 length; /* Length of the buffer segment */
87 };
88 
89 struct cx18_scb {
90  /* These fields form the System Control Block which is used at boot time
91  for localizing the IPC data as well as the code positions for all
92  processors. The offsets are from the start of this struct. */
93 
94  /* Offset where to find the Inter-Processor Communication data */
97  /* Offset where to find the start of the CPU code */
100  /* Offset where to find the start of the APU code */
103  /* Offset where to find the start of the HPU code */
106  /* Offset where to find the start of the PPU code */
109 
110  /* These fields form Inter-Processor Communication data which is used
111  by all processors to locate the information needed for communicating
112  with other processors */
113 
114  /* Fields for CPU: */
115 
116  /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
119  /* Offset to the mailbox used for sending commands from APU to CPU */
121  /* Value to write to register SW1 register set (0xC7003100) after the
122  command is ready */
124  /* Value to write to register SW2 register set (0xC7003140) after the
125  command is cleared */
128 
133 
138 
144 
145  /* Fields for APU: */
146 
153 
158 
163 
169 
170  /* Fields for HPU: */
171 
178 
183 
188 
194 
195  /* Fields for PPU: */
196 
203 
208 
213 
219 
220  /* Fields for EPU: */
221 
228 
233 
238 
244 
245  u32 semaphores[8]; /* Semaphores */
246 
247  u32 reserved50[32]; /* Reserved for future use */
248 
253 
258 
263 
268 
273 
276 };
277 
278 void cx18_init_scb(struct cx18 *cx);
279 
280 #endif