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27 #define MGR_CMD_MASK 0x40000000
30 #define MGR_CMD_MASK_ACK (MGR_CMD_MASK | 0x80000000)
38 #define CX18_CREATE_TASK (MGR_CMD_MASK | 0x0001)
43 #define CX18_DESTROY_TASK (MGR_CMD_MASK | 0x0002)
46 #define CPU_CMD_MASK 0x20000000
47 #define CPU_CMD_MASK_DEBUG (CPU_CMD_MASK | 0x00000000)
48 #define CPU_CMD_MASK_ACK (CPU_CMD_MASK | 0x80000000)
49 #define CPU_CMD_MASK_CAPTURE (CPU_CMD_MASK | 0x00020000)
50 #define CPU_CMD_MASK_TS (CPU_CMD_MASK | 0x00040000)
52 #define EPU_CMD_MASK 0x02000000
53 #define EPU_CMD_MASK_DEBUG (EPU_CMD_MASK | 0x000000)
54 #define EPU_CMD_MASK_DE (EPU_CMD_MASK | 0x040000)
56 #define APU_CMD_MASK 0x10000000
57 #define APU_CMD_MASK_ACK (APU_CMD_MASK | 0x80000000)
59 #define CX18_APU_ENCODING_METHOD_MPEG (0 << 28)
60 #define CX18_APU_ENCODING_METHOD_AC3 (1 << 28)
66 #define CX18_APU_START (APU_CMD_MASK | 0x01)
71 #define CX18_APU_STOP (APU_CMD_MASK | 0x02)
75 #define CX18_APU_RESETAI (APU_CMD_MASK | 0x05)
83 #define CX18_EPU_DMA_DONE (EPU_CMD_MASK_DE | 0x0001)
89 #define CX18_EPU_DEBUG (EPU_CMD_MASK_DEBUG | 0x0003)
94 #define CX18_CPU_DEBUG_PEEK32 (CPU_CMD_MASK_DEBUG | 0x0003)
99 #define CX18_CPU_CAPTURE_START (CPU_CMD_MASK_CAPTURE | 0x0002)
105 #define CX18_CPU_CAPTURE_STOP (CPU_CMD_MASK_CAPTURE | 0x0003)
110 #define CX18_CPU_CAPTURE_PAUSE (CPU_CMD_MASK_CAPTURE | 0x0007)
115 #define CX18_CPU_CAPTURE_RESUME (CPU_CMD_MASK_CAPTURE | 0x0008)
117 #define CAPTURE_CHANNEL_TYPE_NONE 0
118 #define CAPTURE_CHANNEL_TYPE_MPEG 1
119 #define CAPTURE_CHANNEL_TYPE_INDEX 2
120 #define CAPTURE_CHANNEL_TYPE_YUV 3
121 #define CAPTURE_CHANNEL_TYPE_PCM 4
122 #define CAPTURE_CHANNEL_TYPE_VBI 5
123 #define CAPTURE_CHANNEL_TYPE_SLICED_VBI 6
124 #define CAPTURE_CHANNEL_TYPE_TS 7
125 #define CAPTURE_CHANNEL_TYPE_MAX 15
132 #define CX18_CPU_SET_CHANNEL_TYPE (CPU_CMD_MASK_CAPTURE + 1)
138 #define CX18_CPU_SET_STREAM_OUTPUT_TYPE (CPU_CMD_MASK_CAPTURE | 0x0012)
148 #define CX18_CPU_SET_VIDEO_IN (CPU_CMD_MASK_CAPTURE | 0x0004)
157 #define CX18_CPU_SET_VIDEO_RATE (CPU_CMD_MASK_CAPTURE | 0x0005)
164 #define CX18_CPU_SET_VIDEO_RESOLUTION (CPU_CMD_MASK_CAPTURE | 0x0006)
174 #define CX18_CPU_SET_FILTER_PARAM (CPU_CMD_MASK_CAPTURE | 0x0009)
182 #define CX18_CPU_SET_SPATIAL_FILTER_TYPE (CPU_CMD_MASK_CAPTURE | 0x000C)
191 #define CX18_CPU_SET_MEDIAN_CORING (CPU_CMD_MASK_CAPTURE | 0x000E)
200 #define CX18_CPU_SET_INDEXTABLE (CPU_CMD_MASK_CAPTURE | 0x0010)
206 #define CX18_CPU_SET_AUDIO_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0011)
215 #define CX18_CPU_SET_VIDEO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0013)
221 #define CX18_CPU_SET_AUDIO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0014)
237 #define CX18_CPU_SET_MISC_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0015)
249 #define CX18_CPU_SET_RAW_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0016)
256 #define CX18_CPU_SET_CAPTURE_LINE_NO (CPU_CMD_MASK_CAPTURE | 0x0017)
262 #define CX18_CPU_SET_COPYRIGHT (CPU_CMD_MASK_CAPTURE | 0x0018)
268 #define CX18_CPU_SET_AUDIO_PID (CPU_CMD_MASK_CAPTURE | 0x0019)
274 #define CX18_CPU_SET_VIDEO_PID (CPU_CMD_MASK_CAPTURE | 0x001A)
280 #define CX18_CPU_SET_VER_CROP_LINE (CPU_CMD_MASK_CAPTURE | 0x001B)
287 #define CX18_CPU_SET_GOP_STRUCTURE (CPU_CMD_MASK_CAPTURE | 0x001C)
293 #define CX18_CPU_SET_SCENE_CHANGE_DETECTION (CPU_CMD_MASK_CAPTURE | 0x001D)
299 #define CX18_CPU_SET_ASPECT_RATIO (CPU_CMD_MASK_CAPTURE | 0x001E)
305 #define CX18_CPU_SET_SKIP_INPUT_FRAME (CPU_CMD_MASK_CAPTURE | 0x001F)
322 #define CX18_CPU_SET_SLICED_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0020)
329 #define CX18_CPU_SET_USERDATA_PLACE_HOLDER (CPU_CMD_MASK_CAPTURE | 0x0021)
343 #define CX18_CPU_GET_ENC_PTS (CPU_CMD_MASK_CAPTURE | 0x0022)
349 #define CX18_CPU_SET_VFC_PARAM (CPU_CMD_MASK_CAPTURE | 0x0023)
352 #define CPU_CMD_MASK_DE (CPU_CMD_MASK | 0x040000)
358 #define CPU_CMD_DE_SetBase (CPU_CMD_MASK_DE | 0x0001)
368 #define CX18_CPU_DE_SET_MDL_ACK (CPU_CMD_MASK_DE | 0x0002)
377 #define CX18_CPU_DE_SET_MDL (CPU_CMD_MASK_DE | 0x0005)
383 #define CX18_CPU_DE_RELEASE_MDL (CPU_CMD_MASK_DE | 0x0006)
394 #define CNXT_OK 0x000000
397 #define CXERR_UNK_CMD 0x000001
400 #define CXERR_INVALID_PARAM1 0x000002
403 #define CXERR_INVALID_PARAM2 0x000003
406 #define CXERR_DEV_NOT_FOUND 0x000004
409 #define CXERR_NOTSUPPORTED 0x000005
412 #define CXERR_BADPTR 0x000006
415 #define CXERR_NOMEM 0x000007
418 #define CXERR_LINK 0x000008
421 #define CXERR_BUSY 0x000009
424 #define CXERR_NOT_OPEN 0x00000A
427 #define CXERR_OUTOFRANGE 0x00000B
430 #define CXERR_OVERFLOW 0x00000C
433 #define CXERR_BADVER 0x00000D
436 #define CXERR_TIMEOUT 0x00000E
439 #define CXERR_ABORT 0x00000F
442 #define CXERR_I2CDEV_NOTFOUND 0x000010
445 #define CXERR_I2CDEV_XFERERR 0x000011
448 #define CXERR_CHANNELNOTREADY 0x000012
451 #define CXERR_PPU_MB_CORRUPT 0x000013
454 #define CXERR_CPU_MB_CORRUPT 0x000014
457 #define CXERR_APU_MB_CORRUPT 0x000015
460 #define CXERR_FILE_OPEN_READ 0x000016
463 #define CXERR_FILE_OPEN_WRITE 0x000017
466 #define CXERR_I2C_BADSECTION 0x000018
469 #define CXERR_I2CDEV_DATALOW 0x000019
472 #define CXERR_I2CDEV_CLOCKLOW 0x00001A
475 #define CXERR_NO_HW_I2C_INTR 0x00001B
478 #define CXERR_RPU_NOT_READY 0x00001C
481 #define CXERR_RPU_NO_ACK 0x00001D
484 #define CXERR_NODATA_AGAIN 0x00001E
487 #define CXERR_STOPPING_STATUS 0x00001F
490 #define CXERR_DEVPOWER_OFF 0x000020