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descs.h
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1 /*******************************************************************************
2  Header File to describe the DMA descriptors.
3  Enhanced descriptors have been in case of DWMAC1000 Cores.
4 
5  This program is free software; you can redistribute it and/or modify it
6  under the terms and conditions of the GNU General Public License,
7  version 2, as published by the Free Software Foundation.
8 
9  This program is distributed in the hope it will be useful, but WITHOUT
10  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  more details.
13 
14  You should have received a copy of the GNU General Public License along with
15  this program; if not, write to the Free Software Foundation, Inc.,
16  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 
18  The full GNU General Public License is included in this distribution in
19  the file called "COPYING".
20 
21  Author: Giuseppe Cavallaro <[email protected]>
22 *******************************************************************************/
23 
24 #ifndef __DESCS_H__
25 #define __DESCS_H__
26 
27 struct dma_desc {
28  /* Receive descriptor */
29  union {
30  struct {
31  /* RDES0 */
32  u32 payload_csum_error:1;
33  u32 crc_error:1;
34  u32 dribbling:1;
35  u32 mii_error:1;
36  u32 receive_watchdog:1;
37  u32 frame_type:1;
38  u32 collision:1;
39  u32 ipc_csum_error:1;
40  u32 last_descriptor:1;
41  u32 first_descriptor:1;
42  u32 vlan_tag:1;
43  u32 overflow_error:1;
44  u32 length_error:1;
45  u32 sa_filter_fail:1;
46  u32 descriptor_error:1;
47  u32 error_summary:1;
48  u32 frame_length:14;
49  u32 da_filter_fail:1;
50  u32 own:1;
51  /* RDES1 */
52  u32 buffer1_size:11;
53  u32 buffer2_size:11;
54  u32 reserved1:2;
55  u32 second_address_chained:1;
56  u32 end_ring:1;
57  u32 reserved2:5;
58  u32 disable_ic:1;
59 
60  } rx;
61  struct {
62  /* RDES0 */
63  u32 payload_csum_error:1;
64  u32 crc_error:1;
65  u32 dribbling:1;
66  u32 error_gmii:1;
67  u32 receive_watchdog:1;
68  u32 frame_type:1;
69  u32 late_collision:1;
70  u32 ipc_csum_error:1;
71  u32 last_descriptor:1;
72  u32 first_descriptor:1;
73  u32 vlan_tag:1;
74  u32 overflow_error:1;
75  u32 length_error:1;
76  u32 sa_filter_fail:1;
77  u32 descriptor_error:1;
78  u32 error_summary:1;
79  u32 frame_length:14;
80  u32 da_filter_fail:1;
81  u32 own:1;
82  /* RDES1 */
83  u32 buffer1_size:13;
84  u32 reserved1:1;
85  u32 second_address_chained:1;
86  u32 end_ring:1;
87  u32 buffer2_size:13;
88  u32 reserved2:2;
89  u32 disable_ic:1;
90  } erx; /* -- enhanced -- */
91 
92  /* Transmit descriptor */
93  struct {
94  /* TDES0 */
95  u32 deferred:1;
96  u32 underflow_error:1;
97  u32 excessive_deferral:1;
98  u32 collision_count:4;
99  u32 vlan_frame:1;
100  u32 excessive_collisions:1;
101  u32 late_collision:1;
102  u32 no_carrier:1;
103  u32 loss_carrier:1;
104  u32 payload_error:1;
105  u32 frame_flushed:1;
106  u32 jabber_timeout:1;
107  u32 error_summary:1;
108  u32 ip_header_error:1;
109  u32 time_stamp_status:1;
110  u32 reserved1:13;
111  u32 own:1;
112  /* TDES1 */
113  u32 buffer1_size:11;
114  u32 buffer2_size:11;
115  u32 time_stamp_enable:1;
116  u32 disable_padding:1;
117  u32 second_address_chained:1;
118  u32 end_ring:1;
119  u32 crc_disable:1;
120  u32 checksum_insertion:2;
121  u32 first_segment:1;
122  u32 last_segment:1;
123  u32 interrupt:1;
124  } tx;
125  struct {
126  /* TDES0 */
127  u32 deferred:1;
128  u32 underflow_error:1;
129  u32 excessive_deferral:1;
130  u32 collision_count:4;
131  u32 vlan_frame:1;
132  u32 excessive_collisions:1;
133  u32 late_collision:1;
134  u32 no_carrier:1;
135  u32 loss_carrier:1;
136  u32 payload_error:1;
137  u32 frame_flushed:1;
138  u32 jabber_timeout:1;
139  u32 error_summary:1;
140  u32 ip_header_error:1;
141  u32 time_stamp_status:1;
142  u32 reserved1:2;
143  u32 second_address_chained:1;
144  u32 end_ring:1;
145  u32 checksum_insertion:2;
146  u32 reserved2:1;
147  u32 time_stamp_enable:1;
148  u32 disable_padding:1;
149  u32 crc_disable:1;
150  u32 first_segment:1;
151  u32 last_segment:1;
152  u32 interrupt:1;
153  u32 own:1;
154  /* TDES1 */
155  u32 buffer1_size:13;
156  u32 reserved3:3;
157  u32 buffer2_size:13;
158  u32 reserved4:3;
159  } etx; /* -- enhanced -- */
160  } des01;
161  unsigned int des2;
162  unsigned int des3;
163 };
164 
165 /* Transmit checksum insertion control */
166 enum tdes_csum_insertion {
167  cic_disabled = 0, /* Checksum Insertion Control */
168  cic_only_ip = 1, /* Only IP header */
169  cic_no_pseudoheader = 2, /* IP header but pseudoheader
170  * is not calculated */
171  cic_full = 3, /* IP header and pseudoheader */
172 };
173 
174 #endif /* __DESCS_H__ */
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