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dispc.h
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1 /*
2  * linux/drivers/video/omap2/dss/dispc.h
3  *
4  * Copyright (C) 2011 Texas Instruments
5  * Author: Archit Taneja <[email protected]>
6  *
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License version 2 as published by
10  * the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program. If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #ifndef __OMAP2_DISPC_REG_H
22 #define __OMAP2_DISPC_REG_H
23 
24 /* DISPC common registers */
25 #define DISPC_REVISION 0x0000
26 #define DISPC_SYSCONFIG 0x0010
27 #define DISPC_SYSSTATUS 0x0014
28 #define DISPC_IRQSTATUS 0x0018
29 #define DISPC_IRQENABLE 0x001C
30 #define DISPC_CONTROL 0x0040
31 #define DISPC_CONFIG 0x0044
32 #define DISPC_CAPABLE 0x0048
33 #define DISPC_LINE_STATUS 0x005C
34 #define DISPC_LINE_NUMBER 0x0060
35 #define DISPC_GLOBAL_ALPHA 0x0074
36 #define DISPC_CONTROL2 0x0238
37 #define DISPC_CONFIG2 0x0620
38 #define DISPC_DIVISOR 0x0804
39 #define DISPC_GLOBAL_BUFFER 0x0800
40 #define DISPC_CONTROL3 0x0848
41 #define DISPC_CONFIG3 0x084C
42 
43 /* DISPC overlay registers */
44 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
45  DISPC_BA0_OFFSET(n))
46 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
47  DISPC_BA1_OFFSET(n))
48 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
49  DISPC_BA0_UV_OFFSET(n))
50 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
51  DISPC_BA1_UV_OFFSET(n))
52 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
53  DISPC_POS_OFFSET(n))
54 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
55  DISPC_SIZE_OFFSET(n))
56 #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
57  DISPC_ATTR_OFFSET(n))
58 #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
59  DISPC_ATTR2_OFFSET(n))
60 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
61  DISPC_FIFO_THRESH_OFFSET(n))
62 #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
63  DISPC_FIFO_SIZE_STATUS_OFFSET(n))
64 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
65  DISPC_ROW_INC_OFFSET(n))
66 #define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
67  DISPC_PIX_INC_OFFSET(n))
68 #define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
69  DISPC_WINDOW_SKIP_OFFSET(n))
70 #define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
71  DISPC_TABLE_BA_OFFSET(n))
72 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
73  DISPC_FIR_OFFSET(n))
74 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
75  DISPC_FIR2_OFFSET(n))
76 #define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
77  DISPC_PIC_SIZE_OFFSET(n))
78 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
79  DISPC_ACCU0_OFFSET(n))
80 #define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
81  DISPC_ACCU1_OFFSET(n))
82 #define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
83  DISPC_ACCU2_0_OFFSET(n))
84 #define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
85  DISPC_ACCU2_1_OFFSET(n))
86 #define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
87  DISPC_FIR_COEF_H_OFFSET(n, i))
88 #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
89  DISPC_FIR_COEF_HV_OFFSET(n, i))
90 #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
91  DISPC_FIR_COEF_H2_OFFSET(n, i))
92 #define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
93  DISPC_FIR_COEF_HV2_OFFSET(n, i))
94 #define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
95  DISPC_CONV_COEF_OFFSET(n, i))
96 #define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
97  DISPC_FIR_COEF_V_OFFSET(n, i))
98 #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
99  DISPC_FIR_COEF_V2_OFFSET(n, i))
100 #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
101  DISPC_PRELOAD_OFFSET(n))
102 
103 /* DISPC up/downsampling FIR filter coefficient structure */
104 struct dispc_coef {
105  s8 hc4_vc22;
106  s8 hc3_vc2;
107  u8 hc2_vc1;
108  s8 hc1_vc0;
109  s8 hc0_vc00;
110 };
111 
112 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
113 
114 /* DISPC manager/channel specific registers */
115 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
116 {
117  switch (channel) {
118  case OMAP_DSS_CHANNEL_LCD:
119  return 0x004C;
120  case OMAP_DSS_CHANNEL_DIGIT:
121  return 0x0050;
122  case OMAP_DSS_CHANNEL_LCD2:
123  return 0x03AC;
124  case OMAP_DSS_CHANNEL_LCD3:
125  return 0x0814;
126  default:
127  BUG();
128  return 0;
129  }
130 }
131 
132 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
133 {
134  switch (channel) {
135  case OMAP_DSS_CHANNEL_LCD:
136  return 0x0054;
137  case OMAP_DSS_CHANNEL_DIGIT:
138  return 0x0058;
139  case OMAP_DSS_CHANNEL_LCD2:
140  return 0x03B0;
141  case OMAP_DSS_CHANNEL_LCD3:
142  return 0x0818;
143  default:
144  BUG();
145  return 0;
146  }
147 }
148 
149 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
150 {
151  switch (channel) {
152  case OMAP_DSS_CHANNEL_LCD:
153  return 0x0064;
154  case OMAP_DSS_CHANNEL_DIGIT:
155  BUG();
156  return 0;
157  case OMAP_DSS_CHANNEL_LCD2:
158  return 0x0400;
159  case OMAP_DSS_CHANNEL_LCD3:
160  return 0x0840;
161  default:
162  BUG();
163  return 0;
164  }
165 }
166 
167 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
168 {
169  switch (channel) {
170  case OMAP_DSS_CHANNEL_LCD:
171  return 0x0068;
172  case OMAP_DSS_CHANNEL_DIGIT:
173  BUG();
174  return 0;
175  case OMAP_DSS_CHANNEL_LCD2:
176  return 0x0404;
177  case OMAP_DSS_CHANNEL_LCD3:
178  return 0x0844;
179  default:
180  BUG();
181  return 0;
182  }
183 }
184 
185 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
186 {
187  switch (channel) {
188  case OMAP_DSS_CHANNEL_LCD:
189  return 0x006C;
190  case OMAP_DSS_CHANNEL_DIGIT:
191  BUG();
192  return 0;
193  case OMAP_DSS_CHANNEL_LCD2:
194  return 0x0408;
195  case OMAP_DSS_CHANNEL_LCD3:
196  return 0x083C;
197  default:
198  BUG();
199  return 0;
200  }
201 }
202 
203 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
204 {
205  switch (channel) {
206  case OMAP_DSS_CHANNEL_LCD:
207  return 0x0070;
208  case OMAP_DSS_CHANNEL_DIGIT:
209  BUG();
210  return 0;
211  case OMAP_DSS_CHANNEL_LCD2:
212  return 0x040C;
213  case OMAP_DSS_CHANNEL_LCD3:
214  return 0x0838;
215  default:
216  BUG();
217  return 0;
218  }
219 }
220 
221 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
222 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
223 {
224  switch (channel) {
225  case OMAP_DSS_CHANNEL_LCD:
226  return 0x007C;
227  case OMAP_DSS_CHANNEL_DIGIT:
228  return 0x0078;
229  case OMAP_DSS_CHANNEL_LCD2:
230  return 0x03CC;
231  case OMAP_DSS_CHANNEL_LCD3:
232  return 0x0834;
233  default:
234  BUG();
235  return 0;
236  }
237 }
238 
239 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
240 {
241  switch (channel) {
242  case OMAP_DSS_CHANNEL_LCD:
243  return 0x01D4;
244  case OMAP_DSS_CHANNEL_DIGIT:
245  BUG();
246  return 0;
247  case OMAP_DSS_CHANNEL_LCD2:
248  return 0x03C0;
249  case OMAP_DSS_CHANNEL_LCD3:
250  return 0x0828;
251  default:
252  BUG();
253  return 0;
254  }
255 }
256 
257 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
258 {
259  switch (channel) {
260  case OMAP_DSS_CHANNEL_LCD:
261  return 0x01D8;
262  case OMAP_DSS_CHANNEL_DIGIT:
263  BUG();
264  return 0;
265  case OMAP_DSS_CHANNEL_LCD2:
266  return 0x03C4;
267  case OMAP_DSS_CHANNEL_LCD3:
268  return 0x082C;
269  default:
270  BUG();
271  return 0;
272  }
273 }
274 
275 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
276 {
277  switch (channel) {
278  case OMAP_DSS_CHANNEL_LCD:
279  return 0x01DC;
280  case OMAP_DSS_CHANNEL_DIGIT:
281  BUG();
282  return 0;
283  case OMAP_DSS_CHANNEL_LCD2:
284  return 0x03C8;
285  case OMAP_DSS_CHANNEL_LCD3:
286  return 0x0830;
287  default:
288  BUG();
289  return 0;
290  }
291 }
292 
293 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
294 {
295  switch (channel) {
296  case OMAP_DSS_CHANNEL_LCD:
297  return 0x0220;
298  case OMAP_DSS_CHANNEL_DIGIT:
299  BUG();
300  return 0;
301  case OMAP_DSS_CHANNEL_LCD2:
302  return 0x03BC;
303  case OMAP_DSS_CHANNEL_LCD3:
304  return 0x0824;
305  default:
306  BUG();
307  return 0;
308  }
309 }
310 
311 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
312 {
313  switch (channel) {
314  case OMAP_DSS_CHANNEL_LCD:
315  return 0x0224;
316  case OMAP_DSS_CHANNEL_DIGIT:
317  BUG();
318  return 0;
319  case OMAP_DSS_CHANNEL_LCD2:
320  return 0x03B8;
321  case OMAP_DSS_CHANNEL_LCD3:
322  return 0x0820;
323  default:
324  BUG();
325  return 0;
326  }
327 }
328 
329 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
330 {
331  switch (channel) {
332  case OMAP_DSS_CHANNEL_LCD:
333  return 0x0228;
334  case OMAP_DSS_CHANNEL_DIGIT:
335  BUG();
336  return 0;
337  case OMAP_DSS_CHANNEL_LCD2:
338  return 0x03B4;
339  case OMAP_DSS_CHANNEL_LCD3:
340  return 0x081C;
341  default:
342  BUG();
343  return 0;
344  }
345 }
346 
347 /* DISPC overlay register base addresses */
348 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
349 {
350  switch (plane) {
351  case OMAP_DSS_GFX:
352  return 0x0080;
353  case OMAP_DSS_VIDEO1:
354  return 0x00BC;
355  case OMAP_DSS_VIDEO2:
356  return 0x014C;
357  case OMAP_DSS_VIDEO3:
358  return 0x0300;
359  case OMAP_DSS_WB:
360  return 0x0500;
361  default:
362  BUG();
363  return 0;
364  }
365 }
366 
367 /* DISPC overlay register offsets */
368 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
369 {
370  switch (plane) {
371  case OMAP_DSS_GFX:
372  case OMAP_DSS_VIDEO1:
373  case OMAP_DSS_VIDEO2:
374  return 0x0000;
375  case OMAP_DSS_VIDEO3:
376  case OMAP_DSS_WB:
377  return 0x0008;
378  default:
379  BUG();
380  return 0;
381  }
382 }
383 
384 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
385 {
386  switch (plane) {
387  case OMAP_DSS_GFX:
388  case OMAP_DSS_VIDEO1:
389  case OMAP_DSS_VIDEO2:
390  return 0x0004;
391  case OMAP_DSS_VIDEO3:
392  case OMAP_DSS_WB:
393  return 0x000C;
394  default:
395  BUG();
396  return 0;
397  }
398 }
399 
400 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
401 {
402  switch (plane) {
403  case OMAP_DSS_GFX:
404  BUG();
405  return 0;
406  case OMAP_DSS_VIDEO1:
407  return 0x0544;
408  case OMAP_DSS_VIDEO2:
409  return 0x04BC;
410  case OMAP_DSS_VIDEO3:
411  return 0x0310;
412  case OMAP_DSS_WB:
413  return 0x0118;
414  default:
415  BUG();
416  return 0;
417  }
418 }
419 
420 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
421 {
422  switch (plane) {
423  case OMAP_DSS_GFX:
424  BUG();
425  return 0;
426  case OMAP_DSS_VIDEO1:
427  return 0x0548;
428  case OMAP_DSS_VIDEO2:
429  return 0x04C0;
430  case OMAP_DSS_VIDEO3:
431  return 0x0314;
432  case OMAP_DSS_WB:
433  return 0x011C;
434  default:
435  BUG();
436  return 0;
437  }
438 }
439 
440 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
441 {
442  switch (plane) {
443  case OMAP_DSS_GFX:
444  case OMAP_DSS_VIDEO1:
445  case OMAP_DSS_VIDEO2:
446  return 0x0008;
447  case OMAP_DSS_VIDEO3:
448  return 0x009C;
449  default:
450  BUG();
451  return 0;
452  }
453 }
454 
455 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
456 {
457  switch (plane) {
458  case OMAP_DSS_GFX:
459  case OMAP_DSS_VIDEO1:
460  case OMAP_DSS_VIDEO2:
461  return 0x000C;
462  case OMAP_DSS_VIDEO3:
463  case OMAP_DSS_WB:
464  return 0x00A8;
465  default:
466  BUG();
467  return 0;
468  }
469 }
470 
471 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
472 {
473  switch (plane) {
474  case OMAP_DSS_GFX:
475  return 0x0020;
476  case OMAP_DSS_VIDEO1:
477  case OMAP_DSS_VIDEO2:
478  return 0x0010;
479  case OMAP_DSS_VIDEO3:
480  case OMAP_DSS_WB:
481  return 0x0070;
482  default:
483  BUG();
484  return 0;
485  }
486 }
487 
488 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
489 {
490  switch (plane) {
491  case OMAP_DSS_GFX:
492  BUG();
493  return 0;
494  case OMAP_DSS_VIDEO1:
495  return 0x0568;
496  case OMAP_DSS_VIDEO2:
497  return 0x04DC;
498  case OMAP_DSS_VIDEO3:
499  return 0x032C;
500  case OMAP_DSS_WB:
501  return 0x0310;
502  default:
503  BUG();
504  return 0;
505  }
506 }
507 
508 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
509 {
510  switch (plane) {
511  case OMAP_DSS_GFX:
512  return 0x0024;
513  case OMAP_DSS_VIDEO1:
514  case OMAP_DSS_VIDEO2:
515  return 0x0014;
516  case OMAP_DSS_VIDEO3:
517  case OMAP_DSS_WB:
518  return 0x008C;
519  default:
520  BUG();
521  return 0;
522  }
523 }
524 
525 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
526 {
527  switch (plane) {
528  case OMAP_DSS_GFX:
529  return 0x0028;
530  case OMAP_DSS_VIDEO1:
531  case OMAP_DSS_VIDEO2:
532  return 0x0018;
533  case OMAP_DSS_VIDEO3:
534  case OMAP_DSS_WB:
535  return 0x0088;
536  default:
537  BUG();
538  return 0;
539  }
540 }
541 
542 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
543 {
544  switch (plane) {
545  case OMAP_DSS_GFX:
546  return 0x002C;
547  case OMAP_DSS_VIDEO1:
548  case OMAP_DSS_VIDEO2:
549  return 0x001C;
550  case OMAP_DSS_VIDEO3:
551  case OMAP_DSS_WB:
552  return 0x00A4;
553  default:
554  BUG();
555  return 0;
556  }
557 }
558 
559 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
560 {
561  switch (plane) {
562  case OMAP_DSS_GFX:
563  return 0x0030;
564  case OMAP_DSS_VIDEO1:
565  case OMAP_DSS_VIDEO2:
566  return 0x0020;
567  case OMAP_DSS_VIDEO3:
568  case OMAP_DSS_WB:
569  return 0x0098;
570  default:
571  BUG();
572  return 0;
573  }
574 }
575 
576 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
577 {
578  switch (plane) {
579  case OMAP_DSS_GFX:
580  return 0x0034;
581  case OMAP_DSS_VIDEO1:
582  case OMAP_DSS_VIDEO2:
583  case OMAP_DSS_VIDEO3:
584  BUG();
585  return 0;
586  default:
587  BUG();
588  return 0;
589  }
590 }
591 
592 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
593 {
594  switch (plane) {
595  case OMAP_DSS_GFX:
596  return 0x0038;
597  case OMAP_DSS_VIDEO1:
598  case OMAP_DSS_VIDEO2:
599  case OMAP_DSS_VIDEO3:
600  BUG();
601  return 0;
602  default:
603  BUG();
604  return 0;
605  }
606 }
607 
608 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
609 {
610  switch (plane) {
611  case OMAP_DSS_GFX:
612  BUG();
613  return 0;
614  case OMAP_DSS_VIDEO1:
615  case OMAP_DSS_VIDEO2:
616  return 0x0024;
617  case OMAP_DSS_VIDEO3:
618  case OMAP_DSS_WB:
619  return 0x0090;
620  default:
621  BUG();
622  return 0;
623  }
624 }
625 
626 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
627 {
628  switch (plane) {
629  case OMAP_DSS_GFX:
630  BUG();
631  return 0;
632  case OMAP_DSS_VIDEO1:
633  return 0x0580;
634  case OMAP_DSS_VIDEO2:
635  return 0x055C;
636  case OMAP_DSS_VIDEO3:
637  return 0x0424;
638  case OMAP_DSS_WB:
639  return 0x290;
640  default:
641  BUG();
642  return 0;
643  }
644 }
645 
646 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
647 {
648  switch (plane) {
649  case OMAP_DSS_GFX:
650  BUG();
651  return 0;
652  case OMAP_DSS_VIDEO1:
653  case OMAP_DSS_VIDEO2:
654  return 0x0028;
655  case OMAP_DSS_VIDEO3:
656  case OMAP_DSS_WB:
657  return 0x0094;
658  default:
659  BUG();
660  return 0;
661  }
662 }
663 
664 
665 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
666 {
667  switch (plane) {
668  case OMAP_DSS_GFX:
669  BUG();
670  return 0;
671  case OMAP_DSS_VIDEO1:
672  case OMAP_DSS_VIDEO2:
673  return 0x002C;
674  case OMAP_DSS_VIDEO3:
675  case OMAP_DSS_WB:
676  return 0x0000;
677  default:
678  BUG();
679  return 0;
680  }
681 }
682 
683 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
684 {
685  switch (plane) {
686  case OMAP_DSS_GFX:
687  BUG();
688  return 0;
689  case OMAP_DSS_VIDEO1:
690  return 0x0584;
691  case OMAP_DSS_VIDEO2:
692  return 0x0560;
693  case OMAP_DSS_VIDEO3:
694  return 0x0428;
695  case OMAP_DSS_WB:
696  return 0x0294;
697  default:
698  BUG();
699  return 0;
700  }
701 }
702 
703 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
704 {
705  switch (plane) {
706  case OMAP_DSS_GFX:
707  BUG();
708  return 0;
709  case OMAP_DSS_VIDEO1:
710  case OMAP_DSS_VIDEO2:
711  return 0x0030;
712  case OMAP_DSS_VIDEO3:
713  case OMAP_DSS_WB:
714  return 0x0004;
715  default:
716  BUG();
717  return 0;
718  }
719 }
720 
721 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
722 {
723  switch (plane) {
724  case OMAP_DSS_GFX:
725  BUG();
726  return 0;
727  case OMAP_DSS_VIDEO1:
728  return 0x0588;
729  case OMAP_DSS_VIDEO2:
730  return 0x0564;
731  case OMAP_DSS_VIDEO3:
732  return 0x042C;
733  case OMAP_DSS_WB:
734  return 0x0298;
735  default:
736  BUG();
737  return 0;
738  }
739 }
740 
741 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
742 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
743 {
744  switch (plane) {
745  case OMAP_DSS_GFX:
746  BUG();
747  return 0;
748  case OMAP_DSS_VIDEO1:
749  case OMAP_DSS_VIDEO2:
750  return 0x0034 + i * 0x8;
751  case OMAP_DSS_VIDEO3:
752  case OMAP_DSS_WB:
753  return 0x0010 + i * 0x8;
754  default:
755  BUG();
756  return 0;
757  }
758 }
759 
760 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
761 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
762 {
763  switch (plane) {
764  case OMAP_DSS_GFX:
765  BUG();
766  return 0;
767  case OMAP_DSS_VIDEO1:
768  return 0x058C + i * 0x8;
769  case OMAP_DSS_VIDEO2:
770  return 0x0568 + i * 0x8;
771  case OMAP_DSS_VIDEO3:
772  return 0x0430 + i * 0x8;
773  case OMAP_DSS_WB:
774  return 0x02A0 + i * 0x8;
775  default:
776  BUG();
777  return 0;
778  }
779 }
780 
781 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
782 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
783 {
784  switch (plane) {
785  case OMAP_DSS_GFX:
786  BUG();
787  return 0;
788  case OMAP_DSS_VIDEO1:
789  case OMAP_DSS_VIDEO2:
790  return 0x0038 + i * 0x8;
791  case OMAP_DSS_VIDEO3:
792  case OMAP_DSS_WB:
793  return 0x0014 + i * 0x8;
794  default:
795  BUG();
796  return 0;
797  }
798 }
799 
800 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
801 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
802 {
803  switch (plane) {
804  case OMAP_DSS_GFX:
805  BUG();
806  return 0;
807  case OMAP_DSS_VIDEO1:
808  return 0x0590 + i * 8;
809  case OMAP_DSS_VIDEO2:
810  return 0x056C + i * 0x8;
811  case OMAP_DSS_VIDEO3:
812  return 0x0434 + i * 0x8;
813  case OMAP_DSS_WB:
814  return 0x02A4 + i * 0x8;
815  default:
816  BUG();
817  return 0;
818  }
819 }
820 
821 /* coef index i = {0, 1, 2, 3, 4,} */
822 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
823 {
824  switch (plane) {
825  case OMAP_DSS_GFX:
826  BUG();
827  return 0;
828  case OMAP_DSS_VIDEO1:
829  case OMAP_DSS_VIDEO2:
830  case OMAP_DSS_VIDEO3:
831  case OMAP_DSS_WB:
832  return 0x0074 + i * 0x4;
833  default:
834  BUG();
835  return 0;
836  }
837 }
838 
839 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
840 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
841 {
842  switch (plane) {
843  case OMAP_DSS_GFX:
844  BUG();
845  return 0;
846  case OMAP_DSS_VIDEO1:
847  return 0x0124 + i * 0x4;
848  case OMAP_DSS_VIDEO2:
849  return 0x00B4 + i * 0x4;
850  case OMAP_DSS_VIDEO3:
851  case OMAP_DSS_WB:
852  return 0x0050 + i * 0x4;
853  default:
854  BUG();
855  return 0;
856  }
857 }
858 
859 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
860 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
861 {
862  switch (plane) {
863  case OMAP_DSS_GFX:
864  BUG();
865  return 0;
866  case OMAP_DSS_VIDEO1:
867  return 0x05CC + i * 0x4;
868  case OMAP_DSS_VIDEO2:
869  return 0x05A8 + i * 0x4;
870  case OMAP_DSS_VIDEO3:
871  return 0x0470 + i * 0x4;
872  case OMAP_DSS_WB:
873  return 0x02E0 + i * 0x4;
874  default:
875  BUG();
876  return 0;
877  }
878 }
879 
880 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
881 {
882  switch (plane) {
883  case OMAP_DSS_GFX:
884  return 0x01AC;
885  case OMAP_DSS_VIDEO1:
886  return 0x0174;
887  case OMAP_DSS_VIDEO2:
888  return 0x00E8;
889  case OMAP_DSS_VIDEO3:
890  return 0x00A0;
891  default:
892  BUG();
893  return 0;
894  }
895 }
896 #endif
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