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dp83640_reg.h
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1 /* dp83640_reg.h
2  * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011
3  */
4 #ifndef HAVE_DP83640_REGISTERS
5 #define HAVE_DP83640_REGISTERS
6 
7 #define PAGE0 0x0000
8 #define PHYCR2 0x001c /* PHY Control Register 2 */
9 
10 #define PAGE4 0x0004
11 #define PTP_CTL 0x0014 /* PTP Control Register */
12 #define PTP_TDR 0x0015 /* PTP Time Data Register */
13 #define PTP_STS 0x0016 /* PTP Status Register */
14 #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
15 #define PTP_RATEL 0x0018 /* PTP Rate Low Register */
16 #define PTP_RATEH 0x0019 /* PTP Rate High Register */
17 #define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
18 #define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
19 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
20 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
21 #define PTP_ESTS 0x001e /* PTP Event Status Register */
22 #define PTP_EDATA 0x001f /* PTP Event Data Register */
23 
24 #define PAGE5 0x0005
25 #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
26 #define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
27 #define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
28 #define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
29 #define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
30 #define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
31 #define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
32 #define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
33 #define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
34 #define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
35 #define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
36 #define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
37 
38 #define PAGE6 0x0006
39 #define PTP_COC 0x0014 /* PTP Clock Output Control Register */
40 #define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
41 #define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
42 #define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
43 #define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
44 #define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
45 #define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
46 #define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
47 #define PTP_ETR 0x001c /* PTP Ethernet Type Register */
48 #define PTP_OFF 0x001d /* PTP Offset Register */
49 #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
50 #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
51 
52 /* Bit definitions for the PHYCR2 register */
53 #define BC_WRITE (1<<11) /* Broadcast Write Enable */
54 
55 /* Bit definitions for the PTP_CTL register */
56 #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
57 #define TRIG_SEL_MASK (0x7)
58 #define TRIG_DIS (1<<9) /* Disable PTP Trigger */
59 #define TRIG_EN (1<<8) /* Enable PTP Trigger */
60 #define TRIG_READ (1<<7) /* Read PTP Trigger */
61 #define TRIG_LOAD (1<<6) /* Load PTP Trigger */
62 #define PTP_RD_CLK (1<<5) /* Read PTP Clock */
63 #define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
64 #define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
65 #define PTP_ENABLE (1<<2) /* Enable PTP Clock */
66 #define PTP_DISABLE (1<<1) /* Disable PTP Clock */
67 #define PTP_RESET (1<<0) /* Reset PTP Clock */
68 
69 /* Bit definitions for the PTP_STS register */
70 #define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */
71 #define RXTS_RDY (1<<10) /* Receive Timestamp Ready */
72 #define TRIG_DONE (1<<9) /* PTP Trigger Done */
73 #define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */
74 #define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
75 #define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
76 #define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
77 #define EVENT_IE (1<<0) /* Event Interrupt Enable */
78 
79 /* Bit definitions for the PTP_TSTS register */
80 #define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
81 #define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
82 #define TRIG6_ERROR (1<<13) /* Trigger 6 Error */
83 #define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
84 #define TRIG5_ERROR (1<<11) /* Trigger 5 Error */
85 #define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
86 #define TRIG4_ERROR (1<<9) /* Trigger 4 Error */
87 #define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
88 #define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
89 #define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
90 #define TRIG2_ERROR (1<<5) /* Trigger 2 Error */
91 #define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
92 #define TRIG1_ERROR (1<<3) /* Trigger 1 Error */
93 #define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
94 #define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
95 #define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
96 
97 /* Bit definitions for the PTP_RATEH register */
98 #define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */
99 #define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */
100 #define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
101 #define PTP_RATE_HI_MASK (0x3ff)
102 
103 /* Bit definitions for the PTP_ESTS register */
104 #define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */
105 #define EVNTS_MISSED_MASK (0x7)
106 #define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
107 #define EVNT_TS_LEN_MASK (0x3)
108 #define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */
109 #define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */
110 #define EVNT_NUM_MASK (0x7)
111 #define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */
112 #define EVENT_DET (1<<0) /* PTP Event Detected */
113 
114 /* Bit definitions for the PTP_EDATA register */
115 #define E7_RISE (1<<15) /* Indicates direction of Event 7 */
116 #define E7_DET (1<<14) /* Indicates Event 7 detected */
117 #define E6_RISE (1<<13) /* Indicates direction of Event 6 */
118 #define E6_DET (1<<12) /* Indicates Event 6 detected */
119 #define E5_RISE (1<<11) /* Indicates direction of Event 5 */
120 #define E5_DET (1<<10) /* Indicates Event 5 detected */
121 #define E4_RISE (1<<9) /* Indicates direction of Event 4 */
122 #define E4_DET (1<<8) /* Indicates Event 4 detected */
123 #define E3_RISE (1<<7) /* Indicates direction of Event 3 */
124 #define E3_DET (1<<6) /* Indicates Event 3 detected */
125 #define E2_RISE (1<<5) /* Indicates direction of Event 2 */
126 #define E2_DET (1<<4) /* Indicates Event 2 detected */
127 #define E1_RISE (1<<3) /* Indicates direction of Event 1 */
128 #define E1_DET (1<<2) /* Indicates Event 1 detected */
129 #define E0_RISE (1<<1) /* Indicates direction of Event 0 */
130 #define E0_DET (1<<0) /* Indicates Event 0 detected */
131 
132 /* Bit definitions for the PTP_TRIG register */
133 #define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */
134 #define TRIG_PER (1<<14) /* generate a periodic signal */
135 #define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */
136 #define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
137 #define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
138 #define TRIG_GPIO_MASK (0xf)
139 #define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
140 #define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */
141 #define TRIG_CSEL_MASK (0x7)
142 #define TRIG_WR (1<<0) /* Trigger Configuration Write */
143 
144 /* Bit definitions for the PTP_EVNT register */
145 #define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
146 #define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
147 #define EVNT_SINGLE (1<<12) /* enable single event capture operation */
148 #define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
149 #define EVNT_GPIO_MASK (0xf)
150 #define EVNT_SEL_SHIFT (1) /* Event Select */
151 #define EVNT_SEL_MASK (0x7)
152 #define EVNT_WR (1<<0) /* Event Configuration Write */
153 
154 /* Bit definitions for the PTP_TXCFG0 register */
155 #define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */
156 #define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
157 #define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
158 #define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
159 #define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
160 #define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
161 #define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
162 #define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
163 #define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
164 #define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
165 #define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
166 #define TX_PTP_VER_MASK (0xf)
167 #define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
168 
169 /* Bit definitions for the PTP_TXCFG1 register */
170 #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
171 #define BYTE0_MASK_MASK (0xff)
172 #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
173 #define BYTE0_DATA_MASK (0xff)
174 
175 /* Bit definitions for the PSF_CFG0 register */
176 #define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */
177 #define MAC_SRC_ADD_MASK (0x3)
178 #define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */
179 #define MIN_PRE_MASK (0x7)
180 #define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
181 #define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
182 #define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
183 #define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
184 #define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
185 #define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
186 #define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
187 #define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
188 
189 /* Bit definitions for the PTP_RXCFG0 register */
190 #define DOMAIN_EN (1<<15) /* Domain Match Enable */
191 #define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */
192 #define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
193 #define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
194 #define RX_SLAVE (1<<11) /* Receive Slave Only */
195 #define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
196 #define IP1588_EN_MASK (0xf)
197 #define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
198 #define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
199 #define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
200 #define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
201 #define RX_PTP_VER_MASK (0xf)
202 #define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
203 
204 /* Bit definitions for the PTP_RXCFG1 register */
205 #define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
206 #define BYTE0_MASK_MASK (0xff)
207 #define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
208 #define BYTE0_DATA_MASK (0xff)
209 
210 /* Bit definitions for the PTP_RXCFG3 register */
211 #define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
212 #define TS_MIN_IFG_MASK (0xf)
213 #define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */
214 #define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */
215 #define TS_APPEND (1<<9) /* Append Timestamp for L2 */
216 #define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
217 #define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
218 #define PTP_DOMAIN_MASK (0xff)
219 
220 /* Bit definitions for the PTP_RXCFG4 register */
221 #define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
222 #define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
223 #define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */
224 #define TS_SEC_LEN_MASK (0x3)
225 #define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */
226 #define RXTS_NS_OFF_MASK (0x3f)
227 #define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
228 #define RXTS_SEC_OFF_MASK (0x3f)
229 
230 /* Bit definitions for the PTP_COC register */
231 #define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
232 #define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
233 #define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
234 #define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
235 #define PTP_CLKDIV_MASK (0xff)
236 
237 /* Bit definitions for the PSF_CFG1 register */
238 #define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */
239 #define PTPRESERVED_MASK (0xf)
240 #define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */
241 #define VERSIONPTP_MASK (0xf)
242 #define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */
243 #define TRANSPORT_SPECIFIC_MASK (0xf)
244 #define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
245 #define MESSAGETYPE_MASK (0xf)
246 
247 /* Bit definitions for the PTP_SFDCFG register */
248 #define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
249 #define TX_SFD_GPIO_MASK (0xf)
250 #define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
251 #define RX_SFD_GPIO_MASK (0xf)
252 
253 /* Bit definitions for the PTP_INTCTL register */
254 #define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
255 #define PTP_INT_GPIO_MASK (0xf)
256 
257 /* Bit definitions for the PTP_CLKSRC register */
258 #define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
259 #define CLK_SRC_MASK (0x3)
260 #define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
261 #define CLK_SRC_PER_MASK (0x7f)
262 
263 /* Bit definitions for the PTP_OFF register */
264 #define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
265 #define PTP_OFFSET_MASK (0xff)
266 
267 #endif
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