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pll.c
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1 /*
2  * Copyright 2005-2006 Erik Waling
3  * Copyright 2006 Stephane Marchesin
4  * Copyright 2007-2009 Stuart Bennett
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 
25 #include <subdev/vga.h>
26 #include <subdev/bios.h>
27 #include <subdev/bios/bit.h>
28 #include <subdev/bios/bmp.h>
29 #include <subdev/bios/pll.h>
30 
31 struct pll_mapping {
32  u8 type;
33  u32 reg;
34 };
35 
36 static struct pll_mapping
37 nv04_pll_mapping[] = {
38  { PLL_CORE , 0x680500 },
39  { PLL_MEMORY, 0x680504 },
40  { PLL_VPLL0 , 0x680508 },
41  { PLL_VPLL1 , 0x680520 },
42  {}
43 };
44 
45 static struct pll_mapping
46 nv40_pll_mapping[] = {
47  { PLL_CORE , 0x004000 },
48  { PLL_MEMORY, 0x004020 },
49  { PLL_VPLL0 , 0x680508 },
50  { PLL_VPLL1 , 0x680520 },
51  {}
52 };
53 
54 static struct pll_mapping
55 nv50_pll_mapping[] = {
56  { PLL_CORE , 0x004028 },
57  { PLL_SHADER, 0x004020 },
58  { PLL_UNK03 , 0x004000 },
59  { PLL_MEMORY, 0x004008 },
60  { PLL_UNK40 , 0x00e810 },
61  { PLL_UNK41 , 0x00e818 },
62  { PLL_UNK42 , 0x00e824 },
63  { PLL_VPLL0 , 0x614100 },
64  { PLL_VPLL1 , 0x614900 },
65  {}
66 };
67 
68 static struct pll_mapping
69 nv84_pll_mapping[] = {
70  { PLL_CORE , 0x004028 },
71  { PLL_SHADER, 0x004020 },
72  { PLL_MEMORY, 0x004008 },
73  { PLL_VDEC , 0x004030 },
74  { PLL_UNK41 , 0x00e818 },
75  { PLL_VPLL0 , 0x614100 },
76  { PLL_VPLL1 , 0x614900 },
77  {}
78 };
79 
80 static u16
81 pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
82 {
83  struct bit_entry bit_C;
84 
85  if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) {
86  u16 data = nv_ro16(bios, bit_C.offset + 8);
87  if (data) {
88  *ver = nv_ro08(bios, data + 0);
89  *hdr = nv_ro08(bios, data + 1);
90  *len = nv_ro08(bios, data + 2);
91  *cnt = nv_ro08(bios, data + 3);
92  return data;
93  }
94  }
95 
96  if (bmp_version(bios) >= 0x0524) {
97  u16 data = nv_ro16(bios, bios->bmp_offset + 142);
98  if (data) {
99  *ver = nv_ro08(bios, data + 0);
100  *hdr = 1;
101  *cnt = 1;
102  *len = 0x18;
103  return data;
104  }
105  }
106 
107  *ver = 0x00;
108  return 0x0000;
109 }
110 
111 static struct pll_mapping *
112 pll_map(struct nouveau_bios *bios)
113 {
114  switch (nv_device(bios)->card_type) {
115  case NV_04:
116  case NV_10:
117  case NV_20:
118  case NV_30:
119  return nv04_pll_mapping;
120  break;
121  case NV_40:
122  return nv40_pll_mapping;
123  case NV_50:
124  if (nv_device(bios)->chipset == 0x50)
125  return nv50_pll_mapping;
126  else
127  if (nv_device(bios)->chipset < 0xa3 ||
128  nv_device(bios)->chipset == 0xaa ||
129  nv_device(bios)->chipset == 0xac)
130  return nv84_pll_mapping;
131  default:
132  return NULL;
133  }
134 }
135 
136 static u16
137 pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len)
138 {
139  struct pll_mapping *map;
140  u8 hdr, cnt;
141  u16 data;
142 
143  data = pll_limits_table(bios, ver, &hdr, &cnt, len);
144  if (data && *ver >= 0x30) {
145  data += hdr;
146  while (cnt--) {
147  if (nv_ro32(bios, data + 3) == reg) {
148  *type = nv_ro08(bios, data + 0);
149  return data;
150  }
151  data += *len;
152  }
153  return 0x0000;
154  }
155 
156  map = pll_map(bios);
157  while (map->reg) {
158  if (map->reg == reg && *ver >= 0x20) {
159  u16 addr = (data += hdr);
160  *type = map->type;
161  while (cnt--) {
162  if (nv_ro32(bios, data) == map->reg)
163  return data;
164  data += *len;
165  }
166  return addr;
167  } else
168  if (map->reg == reg) {
169  *type = map->type;
170  return data + 1;
171  }
172  map++;
173  }
174 
175  return 0x0000;
176 }
177 
178 static u16
179 pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len)
180 {
181  struct pll_mapping *map;
182  u8 hdr, cnt;
183  u16 data;
184 
185  data = pll_limits_table(bios, ver, &hdr, &cnt, len);
186  if (data && *ver >= 0x30) {
187  data += hdr;
188  while (cnt--) {
189  if (nv_ro08(bios, data + 0) == type) {
190  *reg = nv_ro32(bios, data + 3);
191  return data;
192  }
193  data += *len;
194  }
195  return 0x0000;
196  }
197 
198  map = pll_map(bios);
199  while (map->reg) {
200  if (map->type == type && *ver >= 0x20) {
201  u16 addr = (data += hdr);
202  *reg = map->reg;
203  while (cnt--) {
204  if (nv_ro32(bios, data) == map->reg)
205  return data;
206  data += *len;
207  }
208  return addr;
209  } else
210  if (map->type == type) {
211  *reg = map->reg;
212  return data + 1;
213  }
214  map++;
215  }
216 
217  return 0x0000;
218 }
219 
220 int
221 nvbios_pll_parse(struct nouveau_bios *bios, u32 type, struct nvbios_pll *info)
222 {
223  u8 ver, len;
224  u32 reg = type;
225  u16 data;
226 
227  if (type > PLL_MAX) {
228  reg = type;
229  data = pll_map_reg(bios, reg, &type, &ver, &len);
230  } else {
231  data = pll_map_type(bios, type, &reg, &ver, &len);
232  }
233 
234  if (ver && !data)
235  return -ENOENT;
236 
237  memset(info, 0, sizeof(*info));
238  info->type = type;
239  info->reg = reg;
240 
241  switch (ver) {
242  case 0x00:
243  break;
244  case 0x10:
245  case 0x11:
246  info->vco1.min_freq = nv_ro32(bios, data + 0);
247  info->vco1.max_freq = nv_ro32(bios, data + 4);
248  info->vco2.min_freq = nv_ro32(bios, data + 8);
249  info->vco2.max_freq = nv_ro32(bios, data + 12);
250  info->vco1.min_inputfreq = nv_ro32(bios, data + 16);
251  info->vco2.min_inputfreq = nv_ro32(bios, data + 20);
252  info->vco1.max_inputfreq = INT_MAX;
253  info->vco2.max_inputfreq = INT_MAX;
254 
255  info->max_p = 0x7;
256  info->max_p_usable = 0x6;
257 
258  /* these values taken from nv30/31/36 */
259  switch (bios->version.chip) {
260  case 0x36:
261  info->vco1.min_n = 0x5;
262  break;
263  default:
264  info->vco1.min_n = 0x1;
265  break;
266  }
267  info->vco1.max_n = 0xff;
268  info->vco1.min_m = 0x1;
269  info->vco1.max_m = 0xd;
270 
271  /*
272  * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
273  * table version (apart from nv35)), N2 is compared to
274  * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
275  * save a comparison
276  */
277  info->vco2.min_n = 0x4;
278  switch (bios->version.chip) {
279  case 0x30:
280  case 0x35:
281  info->vco2.max_n = 0x1f;
282  break;
283  default:
284  info->vco2.max_n = 0x28;
285  break;
286  }
287  info->vco2.min_m = 0x1;
288  info->vco2.max_m = 0x4;
289  break;
290  case 0x20:
291  case 0x21:
292  info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000;
293  info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000;
294  info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000;
295  info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000;
296  info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000;
297  info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000;
298  info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000;
299  info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000;
300  info->vco1.min_n = nv_ro08(bios, data + 20);
301  info->vco1.max_n = nv_ro08(bios, data + 21);
302  info->vco1.min_m = nv_ro08(bios, data + 22);
303  info->vco1.max_m = nv_ro08(bios, data + 23);
304  info->vco2.min_n = nv_ro08(bios, data + 24);
305  info->vco2.max_n = nv_ro08(bios, data + 25);
306  info->vco2.min_m = nv_ro08(bios, data + 26);
307  info->vco2.max_m = nv_ro08(bios, data + 27);
308 
309  info->max_p = nv_ro08(bios, data + 29);
310  info->max_p_usable = info->max_p;
311  if (bios->version.chip < 0x60)
312  info->max_p_usable = 0x6;
313  info->bias_p = nv_ro08(bios, data + 30);
314 
315  if (len > 0x22)
316  info->refclk = nv_ro32(bios, data + 31);
317  break;
318  case 0x30:
319  data = nv_ro16(bios, data + 1);
320 
321  info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
322  info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
323  info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000;
324  info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000;
325  info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000;
326  info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000;
327  info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000;
328  info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000;
329  info->vco1.min_n = nv_ro08(bios, data + 16);
330  info->vco1.max_n = nv_ro08(bios, data + 17);
331  info->vco1.min_m = nv_ro08(bios, data + 18);
332  info->vco1.max_m = nv_ro08(bios, data + 19);
333  info->vco2.min_n = nv_ro08(bios, data + 20);
334  info->vco2.max_n = nv_ro08(bios, data + 21);
335  info->vco2.min_m = nv_ro08(bios, data + 22);
336  info->vco2.max_m = nv_ro08(bios, data + 23);
337  info->max_p_usable = info->max_p = nv_ro08(bios, data + 25);
338  info->bias_p = nv_ro08(bios, data + 27);
339  info->refclk = nv_ro32(bios, data + 28);
340  break;
341  case 0x40:
342  info->refclk = nv_ro16(bios, data + 9) * 1000;
343  data = nv_ro16(bios, data + 1);
344 
345  info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000;
346  info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000;
347  info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000;
348  info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000;
349  info->vco1.min_m = nv_ro08(bios, data + 8);
350  info->vco1.max_m = nv_ro08(bios, data + 9);
351  info->vco1.min_n = nv_ro08(bios, data + 10);
352  info->vco1.max_n = nv_ro08(bios, data + 11);
353  info->min_p = nv_ro08(bios, data + 12);
354  info->max_p = nv_ro08(bios, data + 13);
355  break;
356  default:
357  nv_error(bios, "unknown pll limits version 0x%02x\n", ver);
358  return -EINVAL;
359  }
360 
361  if (!info->refclk) {
362  info->refclk = nv_device(bios)->crystal;
363  if (bios->version.chip == 0x51) {
364  u32 sel_clk = nv_rd32(bios, 0x680524);
365  if ((info->reg == 0x680508 && sel_clk & 0x20) ||
366  (info->reg == 0x680520 && sel_clk & 0x80)) {
367  if (nv_rdvgac(bios, 0, 0x27) < 0xa3)
368  info->refclk = 200000;
369  else
370  info->refclk = 25000;
371  }
372  }
373  }
374 
375  /*
376  * By now any valid limit table ought to have set a max frequency for
377  * vco1, so if it's zero it's either a pre limit table bios, or one
378  * with an empty limit table (seen on nv18)
379  */
380  if (!info->vco1.max_freq) {
381  info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67);
382  info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71);
383  if (bmp_version(bios) < 0x0506) {
384  info->vco1.max_freq = 256000;
385  info->vco1.min_freq = 128000;
386  }
387 
388  info->vco1.min_inputfreq = 0;
389  info->vco1.max_inputfreq = INT_MAX;
390  info->vco1.min_n = 0x1;
391  info->vco1.max_n = 0xff;
392  info->vco1.min_m = 0x1;
393 
394  if (nv_device(bios)->crystal == 13500) {
395  /* nv05 does this, nv11 doesn't, nv10 unknown */
396  if (bios->version.chip < 0x11)
397  info->vco1.min_m = 0x7;
398  info->vco1.max_m = 0xd;
399  } else {
400  if (bios->version.chip < 0x11)
401  info->vco1.min_m = 0x8;
402  info->vco1.max_m = 0xe;
403  }
404 
405  if (bios->version.chip < 0x17 ||
406  bios->version.chip == 0x1a ||
407  bios->version.chip == 0x20)
408  info->max_p = 4;
409  else
410  info->max_p = 5;
411  info->max_p_usable = info->max_p;
412  }
413 
414  return 0;
415 }
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