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meye.h
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1 /*
2  * Motion Eye video4linux driver for Sony Vaio PictureBook
3  *
4  * Copyright (C) 2001-2004 Stelian Pop <[email protected]>
5  *
6  * Copyright (C) 2001-2002 AlcĂ´ve <www.alcove.com>
7  *
8  * Copyright (C) 2000 Andrew Tridgell <[email protected]>
9  *
10  * Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras.
11  *
12  * Some parts borrowed from various video4linux drivers, especially
13  * bttv-driver.c and zoran.c, see original files for credits.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2 of the License, or
18  * (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28  */
29 
30 #ifndef _MEYE_PRIV_H_
31 #define _MEYE_PRIV_H_
32 
33 #define MEYE_DRIVER_MAJORVERSION 1
34 #define MEYE_DRIVER_MINORVERSION 14
35 
36 #define MEYE_DRIVER_VERSION __stringify(MEYE_DRIVER_MAJORVERSION) "." \
37  __stringify(MEYE_DRIVER_MINORVERSION)
38 
39 #include <linux/types.h>
40 #include <linux/pci.h>
41 #include <linux/kfifo.h>
42 
43 /****************************************************************************/
44 /* Motion JPEG chip registers */
45 /****************************************************************************/
46 
47 /* Motion JPEG chip PCI configuration registers */
48 #define MCHIP_PCI_POWER_CSR 0x54
49 #define MCHIP_PCI_MCORE_STATUS 0x60 /* see HIC_STATUS */
50 #define MCHIP_PCI_HOSTUSEREQ_SET 0x64
51 #define MCHIP_PCI_HOSTUSEREQ_CLR 0x68
52 #define MCHIP_PCI_LOWPOWER_SET 0x6c
53 #define MCHIP_PCI_LOWPOWER_CLR 0x70
54 #define MCHIP_PCI_SOFTRESET_SET 0x74
55 
56 /* Motion JPEG chip memory mapped registers */
57 #define MCHIP_MM_REGS 0x200 /* 512 bytes */
58 #define MCHIP_REG_TIMEOUT 1000 /* reg access, ~us */
59 #define MCHIP_MCC_VRJ_TIMEOUT 1000 /* MCC & VRJ access */
60 
61 #define MCHIP_MM_PCI_MODE 0x00 /* PCI access mode */
62 #define MCHIP_MM_PCI_MODE_RETRY 0x00000001 /* retry mode */
63 #define MCHIP_MM_PCI_MODE_MASTER 0x00000002 /* master access */
64 #define MCHIP_MM_PCI_MODE_READ_LINE 0x00000004 /* read line */
65 
66 #define MCHIP_MM_INTA 0x04 /* Int status/mask */
67 #define MCHIP_MM_INTA_MCC 0x00000001 /* MCC interrupt */
68 #define MCHIP_MM_INTA_VRJ 0x00000002 /* VRJ interrupt */
69 #define MCHIP_MM_INTA_HIC_1 0x00000004 /* one frame done */
70 #define MCHIP_MM_INTA_HIC_1_MASK 0x00000400 /* 1: enable */
71 #define MCHIP_MM_INTA_HIC_END 0x00000008 /* all frames done */
72 #define MCHIP_MM_INTA_HIC_END_MASK 0x00000800
73 #define MCHIP_MM_INTA_JPEG 0x00000010 /* decompress. error */
74 #define MCHIP_MM_INTA_JPEG_MASK 0x00001000
75 #define MCHIP_MM_INTA_CAPTURE 0x00000020 /* capture end */
76 #define MCHIP_MM_INTA_PCI_ERR 0x00000040 /* PCI error */
77 #define MCHIP_MM_INTA_PCI_ERR_MASK 0x00004000
78 
79 #define MCHIP_MM_PT_ADDR 0x08 /* page table address*/
80  /* n*4kB */
81 #define MCHIP_NB_PAGES 1024 /* pages for display */
82 #define MCHIP_NB_PAGES_MJPEG 256 /* pages for mjpeg */
83 
84 #define MCHIP_MM_FIR(n) (0x0c+(n)*4) /* Frame info 0-3 */
85 #define MCHIP_MM_FIR_RDY 0x00000001 /* frame ready */
86 #define MCHIP_MM_FIR_FAILFR_MASK 0xf8000000 /* # of failed frames */
87 #define MCHIP_MM_FIR_FAILFR_SHIFT 27
88 
89  /* continuous comp/decomp mode */
90 #define MCHIP_MM_FIR_C_ENDL_MASK 0x000007fe /* end DW [10] */
91 #define MCHIP_MM_FIR_C_ENDL_SHIFT 1
92 #define MCHIP_MM_FIR_C_ENDP_MASK 0x0007f800 /* end page [8] */
93 #define MCHIP_MM_FIR_C_ENDP_SHIFT 11
94 #define MCHIP_MM_FIR_C_STARTP_MASK 0x07f80000 /* start page [8] */
95 #define MCHIP_MM_FIR_C_STARTP_SHIFT 19
96 
97  /* continuous picture output mode */
98 #define MCHIP_MM_FIR_O_STARTP_MASK 0x7ffe0000 /* start page [10] */
99 #define MCHIP_MM_FIR_O_STARTP_SHIFT 17
100 
101 #define MCHIP_MM_FIFO_DATA 0x1c /* PCI TGT FIFO data */
102 #define MCHIP_MM_FIFO_STATUS 0x20 /* PCI TGT FIFO stat */
103 #define MCHIP_MM_FIFO_MASK 0x00000003
104 #define MCHIP_MM_FIFO_WAIT_OR_READY 0x00000002 /* Bits common to WAIT & READY*/
105 #define MCHIP_MM_FIFO_IDLE 0x0 /* HIC idle */
106 #define MCHIP_MM_FIFO_IDLE1 0x1 /* idem ??? */
107 #define MCHIP_MM_FIFO_WAIT 0x2 /* wait request */
108 #define MCHIP_MM_FIFO_READY 0x3 /* data ready */
109 
110 #define MCHIP_HIC_HOST_USEREQ 0x40 /* host uses MCORE */
111 
112 #define MCHIP_HIC_TP_BUSY 0x44 /* taking picture */
113 
114 #define MCHIP_HIC_PIC_SAVED 0x48 /* pic in SDRAM */
115 
116 #define MCHIP_HIC_LOWPOWER 0x4c /* clock stopped */
117 
118 #define MCHIP_HIC_CTL 0x50 /* HIC control */
119 #define MCHIP_HIC_CTL_SOFT_RESET 0x00000001 /* MCORE reset */
120 #define MCHIP_HIC_CTL_MCORE_RDY 0x00000002 /* MCORE ready */
121 
122 #define MCHIP_HIC_CMD 0x54 /* HIC command */
123 #define MCHIP_HIC_CMD_BITS 0x00000003 /* cmd width=[1:0]*/
124 #define MCHIP_HIC_CMD_NOOP 0x0
125 #define MCHIP_HIC_CMD_START 0x1
126 #define MCHIP_HIC_CMD_STOP 0x2
127 
128 #define MCHIP_HIC_MODE 0x58
129 #define MCHIP_HIC_MODE_NOOP 0x0
130 #define MCHIP_HIC_MODE_STILL_CAP 0x1 /* still pic capt */
131 #define MCHIP_HIC_MODE_DISPLAY 0x2 /* display */
132 #define MCHIP_HIC_MODE_STILL_COMP 0x3 /* still pic comp. */
133 #define MCHIP_HIC_MODE_STILL_DECOMP 0x4 /* still pic decomp. */
134 #define MCHIP_HIC_MODE_CONT_COMP 0x5 /* cont capt+comp */
135 #define MCHIP_HIC_MODE_CONT_DECOMP 0x6 /* cont decomp+disp */
136 #define MCHIP_HIC_MODE_STILL_OUT 0x7 /* still pic output */
137 #define MCHIP_HIC_MODE_CONT_OUT 0x8 /* cont output */
138 
139 #define MCHIP_HIC_STATUS 0x5c
140 #define MCHIP_HIC_STATUS_MCC_RDY 0x00000001 /* MCC reg acc ok */
141 #define MCHIP_HIC_STATUS_VRJ_RDY 0x00000002 /* VRJ reg acc ok */
142 #define MCHIP_HIC_STATUS_IDLE 0x00000003
143 #define MCHIP_HIC_STATUS_CAPDIS 0x00000004 /* cap/disp in prog */
144 #define MCHIP_HIC_STATUS_COMPDEC 0x00000008 /* (de)comp in prog */
145 #define MCHIP_HIC_STATUS_BUSY 0x00000010 /* HIC busy */
146 
147 #define MCHIP_HIC_S_RATE 0x60 /* MJPEG # frames */
148 
149 #define MCHIP_HIC_PCI_VFMT 0x64 /* video format */
150 #define MCHIP_HIC_PCI_VFMT_YVYU 0x00000001 /* 0: V Y' U Y */
151  /* 1: Y' V Y U */
152 
153 #define MCHIP_MCC_CMD 0x80 /* MCC commands */
154 #define MCHIP_MCC_CMD_INITIAL 0x0 /* idle ? */
155 #define MCHIP_MCC_CMD_IIC_START_SET 0x1
156 #define MCHIP_MCC_CMD_IIC_END_SET 0x2
157 #define MCHIP_MCC_CMD_FM_WRITE 0x3 /* frame memory */
158 #define MCHIP_MCC_CMD_FM_READ 0x4
159 #define MCHIP_MCC_CMD_FM_STOP 0x5
160 #define MCHIP_MCC_CMD_CAPTURE 0x6
161 #define MCHIP_MCC_CMD_DISPLAY 0x7
162 #define MCHIP_MCC_CMD_END_DISP 0x8
163 #define MCHIP_MCC_CMD_STILL_COMP 0x9
164 #define MCHIP_MCC_CMD_STILL_DECOMP 0xa
165 #define MCHIP_MCC_CMD_STILL_OUTPUT 0xb
166 #define MCHIP_MCC_CMD_CONT_OUTPUT 0xc
167 #define MCHIP_MCC_CMD_CONT_COMP 0xd
168 #define MCHIP_MCC_CMD_CONT_DECOMP 0xe
169 #define MCHIP_MCC_CMD_RESET 0xf /* MCC reset */
170 
171 #define MCHIP_MCC_IIC_WR 0x84
172 
173 #define MCHIP_MCC_MCC_WR 0x88
174 
175 #define MCHIP_MCC_MCC_RD 0x8c
176 
177 #define MCHIP_MCC_STATUS 0x90
178 #define MCHIP_MCC_STATUS_CAPT 0x00000001 /* capturing */
179 #define MCHIP_MCC_STATUS_DISP 0x00000002 /* displaying */
180 #define MCHIP_MCC_STATUS_COMP 0x00000004 /* compressing */
181 #define MCHIP_MCC_STATUS_DECOMP 0x00000008 /* decompressing */
182 #define MCHIP_MCC_STATUS_MCC_WR 0x00000010 /* register ready */
183 #define MCHIP_MCC_STATUS_MCC_RD 0x00000020 /* register ready */
184 #define MCHIP_MCC_STATUS_IIC_WR 0x00000040 /* register ready */
185 #define MCHIP_MCC_STATUS_OUTPUT 0x00000080 /* output in prog */
186 
187 #define MCHIP_MCC_SIG_POLARITY 0x94
188 #define MCHIP_MCC_SIG_POL_VS_H 0x00000001 /* VS active-high */
189 #define MCHIP_MCC_SIG_POL_HS_H 0x00000002 /* HS active-high */
190 #define MCHIP_MCC_SIG_POL_DOE_H 0x00000004 /* DOE active-high */
191 
192 #define MCHIP_MCC_IRQ 0x98
193 #define MCHIP_MCC_IRQ_CAPDIS_STRT 0x00000001 /* cap/disp started */
194 #define MCHIP_MCC_IRQ_CAPDIS_STRT_MASK 0x00000010
195 #define MCHIP_MCC_IRQ_CAPDIS_END 0x00000002 /* cap/disp ended */
196 #define MCHIP_MCC_IRQ_CAPDIS_END_MASK 0x00000020
197 #define MCHIP_MCC_IRQ_COMPDEC_STRT 0x00000004 /* (de)comp started */
198 #define MCHIP_MCC_IRQ_COMPDEC_STRT_MASK 0x00000040
199 #define MCHIP_MCC_IRQ_COMPDEC_END 0x00000008 /* (de)comp ended */
200 #define MCHIP_MCC_IRQ_COMPDEC_END_MASK 0x00000080
201 
202 #define MCHIP_MCC_HSTART 0x9c /* video in */
203 #define MCHIP_MCC_VSTART 0xa0
204 #define MCHIP_MCC_HCOUNT 0xa4
205 #define MCHIP_MCC_VCOUNT 0xa8
206 #define MCHIP_MCC_R_XBASE 0xac /* capt/disp */
207 #define MCHIP_MCC_R_YBASE 0xb0
208 #define MCHIP_MCC_R_XRANGE 0xb4
209 #define MCHIP_MCC_R_YRANGE 0xb8
210 #define MCHIP_MCC_B_XBASE 0xbc /* comp/decomp */
211 #define MCHIP_MCC_B_YBASE 0xc0
212 #define MCHIP_MCC_B_XRANGE 0xc4
213 #define MCHIP_MCC_B_YRANGE 0xc8
214 
215 #define MCHIP_MCC_R_SAMPLING 0xcc /* 1: 1:4 */
216 
217 #define MCHIP_VRJ_CMD 0x100 /* VRJ commands */
218 
219 /* VRJ registers (see table 12.2.4) */
220 #define MCHIP_VRJ_COMPRESSED_DATA 0x1b0
221 #define MCHIP_VRJ_PIXEL_DATA 0x1b8
222 
223 #define MCHIP_VRJ_BUS_MODE 0x100
224 #define MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL 0x108
225 #define MCHIP_VRJ_PDAT_USE 0x110
226 #define MCHIP_VRJ_MODE_SPECIFY 0x118
227 #define MCHIP_VRJ_LIMIT_COMPRESSED_LO 0x120
228 #define MCHIP_VRJ_LIMIT_COMPRESSED_HI 0x124
229 #define MCHIP_VRJ_COMP_DATA_FORMAT 0x128
230 #define MCHIP_VRJ_TABLE_DATA 0x140
231 #define MCHIP_VRJ_RESTART_INTERVAL 0x148
232 #define MCHIP_VRJ_NUM_LINES 0x150
233 #define MCHIP_VRJ_NUM_PIXELS 0x158
234 #define MCHIP_VRJ_NUM_COMPONENTS 0x160
235 #define MCHIP_VRJ_SOF1 0x168
236 #define MCHIP_VRJ_SOF2 0x170
237 #define MCHIP_VRJ_SOF3 0x178
238 #define MCHIP_VRJ_SOF4 0x180
239 #define MCHIP_VRJ_SOS 0x188
240 #define MCHIP_VRJ_SOFT_RESET 0x190
241 
242 #define MCHIP_VRJ_STATUS 0x1c0
243 #define MCHIP_VRJ_STATUS_BUSY 0x00001
244 #define MCHIP_VRJ_STATUS_COMP_ACCESS 0x00002
245 #define MCHIP_VRJ_STATUS_PIXEL_ACCESS 0x00004
246 #define MCHIP_VRJ_STATUS_ERROR 0x00008
247 
248 #define MCHIP_VRJ_IRQ_FLAG 0x1c8
249 #define MCHIP_VRJ_ERROR_REPORT 0x1d8
250 
251 #define MCHIP_VRJ_START_COMMAND 0x1a0
252 
253 /****************************************************************************/
254 /* Driver definitions. */
255 /****************************************************************************/
256 
257 /* Sony Programmable I/O Controller for accessing the camera commands */
258 #include <linux/sony-laptop.h>
259 
260 /* private API definitions */
261 #include <linux/meye.h>
262 #include <linux/mutex.h>
263 
264 
265 /* Enable jpg software correction */
266 #define MEYE_JPEG_CORRECTION 1
267 
268 /* Maximum size of a buffer */
269 #define MEYE_MAX_BUFSIZE 614400 /* 640 * 480 * 2 */
270 
271 /* Maximum number of buffers */
272 #define MEYE_MAX_BUFNBRS 32
273 
274 /* State of a buffer */
275 #define MEYE_BUF_UNUSED 0 /* not used */
276 #define MEYE_BUF_USING 1 /* currently grabbing / playing */
277 #define MEYE_BUF_DONE 2 /* done */
278 
279 /* grab buffer */
281  int state; /* state of buffer */
282  unsigned long size; /* size of jpg frame */
283  struct timeval timestamp; /* timestamp */
284  unsigned long sequence; /* sequence number */
285 };
286 
287 /* size of kfifos containings buffer indices */
288 #define MEYE_QUEUE_SIZE MEYE_MAX_BUFNBRS
289 
290 /* Motion Eye device structure */
291 struct meye {
292  struct v4l2_device v4l2_dev; /* Main v4l2_device struct */
293  struct pci_dev *mchip_dev; /* pci device */
294  u8 mchip_irq; /* irq */
295  u8 mchip_mode; /* actual mchip mode: HIC_MODE... */
296  u8 mchip_fnum; /* current mchip frame number */
297  unsigned char __iomem *mchip_mmregs;/* mchip: memory mapped registers */
298  u8 *mchip_ptable[MCHIP_NB_PAGES];/* mchip: ptable */
299  void *mchip_ptable_toc; /* mchip: ptable toc */
300  dma_addr_t mchip_dmahandle; /* mchip: dma handle to ptable toc */
301  unsigned char *grab_fbuffer; /* capture framebuffer */
302  unsigned char *grab_temp; /* temporary buffer */
303  /* list of buffers */
305  int vma_use_count[MEYE_MAX_BUFNBRS]; /* mmap count */
306  struct mutex lock; /* mutex for open/mmap... */
307  struct kfifo grabq; /* queue for buffers to be grabbed */
308  spinlock_t grabq_lock; /* lock protecting the queue */
309  struct kfifo doneq; /* queue for grabbed buffers */
310  spinlock_t doneq_lock; /* lock protecting the queue */
311  wait_queue_head_t proc_list; /* wait queue */
312  struct video_device *vdev; /* video device parameters */
317  struct meye_params params; /* additional parameters */
318  unsigned long in_use; /* set to 1 if the device is in use */
319 #ifdef CONFIG_PM
320  u8 pm_mchip_mode; /* old mchip mode */
321 #endif
322 };
323 
324 #endif